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Initial commit for Socionext UniPhier SoC support. BL1, Bl2, and BL31 are supported. Refer to docs/plat/socionext-uniphier.md for more detais. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
29 lines
610 B
ArmAsm
29 lines
610 B
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.globl uniphier_warmboot_entrypoint
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.globl uniphier_fake_pwr_down
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func uniphier_warmboot_entrypoint
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mrs x0, mpidr_el1
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mov_imm x1, MPIDR_AFFINITY_MASK
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and x0, x0, x1
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b 1f
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0: wfe
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1: ldr x1, uniphier_holding_pen_release
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cmp x1, x0
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b.ne 0b
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ldr x0, uniphier_sec_entrypoint
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br x0
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endfunc uniphier_warmboot_entrypoint
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func uniphier_fake_pwr_down
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bl disable_mmu_icache_el3
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b uniphier_warmboot_entrypoint
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endfunc uniphier_fake_pwr_down
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