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https://github.com/ARM-software/arm-trusted-firmware.git
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658b3154d5
At the moment we access the RSB bus on all Allwinner H6 boards unconditionally, even though some boards do not have any PMIC at all, while others have some I2C devices connected to the same pins. The latter case is just fragile, but the first case leads to a hang on at least one board, as reported by Jernej. Scan the devicetree, to check for the availability of the RSB bus node. Proceed only if the RSB DT node is actually enabled. Change-Id: Iea7dcfe3e085e173334d098ec4ddcb6c4b085771 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Jernej Skrabec <jernej.skrabec@gmail.com>
126 lines
2.6 KiB
C
126 lines
2.6 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/allwinner/axp.h>
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#include <drivers/allwinner/sunxi_rsb.h>
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#include <libfdt.h>
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#include <lib/mmio.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_def.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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#define AXP805_HW_ADDR 0x745
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#define AXP805_RT_ADDR 0x3a
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static enum pmic_type {
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UNKNOWN,
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AXP805,
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} pmic;
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int axp_read(uint8_t reg)
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{
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return rsb_read(AXP805_RT_ADDR, reg);
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}
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int axp_write(uint8_t reg, uint8_t val)
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{
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return rsb_write(AXP805_RT_ADDR, reg, val);
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}
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static int rsb_init(void)
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{
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int ret;
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ret = rsb_init_controller();
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if (ret)
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return ret;
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/* Switch to the recommended 3 MHz bus clock. */
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ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
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if (ret)
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return ret;
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/* Initiate an I2C transaction to switch the PMIC to RSB mode. */
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ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
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if (ret)
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return ret;
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/* Associate the 8-bit runtime address with the 12-bit bus address. */
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ret = rsb_assign_runtime_address(AXP805_HW_ADDR, AXP805_RT_ADDR);
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if (ret)
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return ret;
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return axp_check_id();
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}
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int sunxi_pmic_setup(uint16_t socid, const void *fdt)
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{
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int node, ret;
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node = fdt_node_offset_by_compatible(fdt, 0, "allwinner,sun8i-a23-rsb");
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if ((node < 0) || !fdt_node_is_enabled(fdt, node)) {
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return -ENODEV;
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}
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INFO("PMIC: Probing AXP805 on RSB\n");
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ret = sunxi_init_platform_r_twi(socid, true);
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if (ret)
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return ret;
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ret = rsb_init();
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if (ret)
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return ret;
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/* Switch the AXP805 to master/single-PMIC mode. */
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ret = axp_write(0xff, 0x0);
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if (ret)
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return ret;
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pmic = AXP805;
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axp_setup_regulators(fdt);
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/* Switch the PMIC back to I2C mode. */
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ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
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if (ret)
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return ret;
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return 0;
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}
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void sunxi_power_down(void)
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{
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switch (pmic) {
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case AXP805:
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/* (Re-)init RSB in case the rich OS has disabled it. */
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sunxi_init_platform_r_twi(SUNXI_SOC_H6, true);
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rsb_init();
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axp_power_off();
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break;
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default:
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break;
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}
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}
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void sunxi_cpu_power_off_self(void)
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{
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u_register_t mpidr = read_mpidr();
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unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
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/* Enable the CPUIDLE hardware (only really needs to be done once). */
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mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000);
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mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001);
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/* Trigger power off for this core. */
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mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core));
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}
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