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The Allwinner H616 and its siblings come in different die revisions, some have 256 KB of L2 cache, some have 1 MB. This prevents a single static cache description in the devicetree. Use the cache size ID register (CCSIDR_EL1) to query the topology of the L2 cache, and adjust the cache-sets and cache-size properties in the L2 cache DT node accordingly. The ARM ARM does not promise (anymore) that the cache size can be derived *architecturally* from this register, but the reading is definitely correct for the Arm Cortex-A53 core used. Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
54 lines
1.1 KiB
C
54 lines
1.1 KiB
C
/*
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* Copyright (c) 2021, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <libfdt.h>
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#include <common/debug.h>
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#include <common/fdt_fixup.h>
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#include <common/fdt_wrappers.h>
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#include <sunxi_private.h>
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void sunxi_prepare_dtb(void *fdt)
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{
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int ret;
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if (fdt == NULL || fdt_check_header(fdt) != 0) {
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return;
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}
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ret = fdt_open_into(fdt, fdt, 0x10000);
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if (ret < 0) {
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ERROR("Preparing devicetree at %p: error %d\n", fdt, ret);
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return;
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}
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#ifdef SUNXI_BL31_IN_DRAM
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/* Reserve memory used by Trusted Firmware. */
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if (fdt_add_reserved_memory(fdt, "tf-a@40000000", BL31_BASE,
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BL31_LIMIT - BL31_BASE)) {
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WARN("Failed to add reserved memory nodes to DT.\n");
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}
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#endif
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sunxi_soc_fdt_fixup(fdt);
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if (sunxi_psci_is_scpi()) {
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ret = fdt_add_cpu_idle_states(fdt, sunxi_idle_states);
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if (ret < 0) {
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WARN("Failed to add idle states to DT: %d\n", ret);
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}
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}
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ret = fdt_pack(fdt);
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if (ret < 0) {
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ERROR("Failed to pack devicetree at %p: error %d\n",
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fdt, ret);
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}
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clean_dcache_range((uintptr_t)fdt, fdt_blob_size(fdt));
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INFO("Changed devicetree.\n");
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}
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