Andre Przywara ee5b26fd00 feat(allwinner): adjust H616 L2 cache size in DTB ... The Allwinner H616 and its siblings come in different die revisions, some have 256 KB of L2 cache, some have 1 MB. This prevents a single static cache description in the devicetree. Use the cache size ID register (CCSIDR_EL1) to query the topology of the L2 cache, and adjust the cache-sets and cache-size properties in the L2 cache DT node accordingly. The ARM ARM does not promise (anymore) that the cache size can be derived *architecturally* from this register, but the reading is definitely correct for the Arm Cortex-A53 core used. Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d Signed-off-by: Andre Przywara <andre.przywara@arm.com>		2024-07-09 15:55:23 +02:00
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mentor_i2c_plat.h	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
plat_macros.S	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
platform_def.h	feat(allwinner): choose PSCI states to avoid translation	2022-04-26 17:52:31 +02:00
sunxi_cpucfg_ncat.h	feat(allwinner): add extra CPU control registers	2023-04-26 17:45:29 +01:00
sunxi_cpucfg_ncat2.h	feat(allwinner): add function to detect H616 die variant	2023-04-26 17:45:29 +01:00
sunxi_def.h	feat(allwinner): add function to detect H616 die variant	2023-04-26 17:45:29 +01:00
sunxi_private.h	feat(allwinner): adjust H616 L2 cache size in DTB	2024-07-09 15:55:23 +02:00