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13f4a25251
Patch fc7dca72ba656e5f147487b20f9f0fb6eb39e116 changed the owning
security states of the TRBE and SPE buffers to NS. The thinking was that
this would assist SMCCC feature availability to more easily determine
if the feature is enabled or disabled. However, that only changed bit 0
while the SMCCC feature only looks at bit 1 so this change is redundant.
It was also meant to tighten security but that was done by
73d98e3759 instead.
Annoyingly, FEAT_TRBE has TRBIDR_EL1 which reports that programming is
allowed when the current security state owns the buffer even when the
MDCR_EL3 setting disallows this in practice.
So revert the functional aspect of the patch as it causes linux panics
with ERRATA_A520_2938996. Keep the defines as they are used elsewhere.
Change-Id: I39463d585df89aee44d1996137616da85d678f41
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/extensions/trbe.h>
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void trbe_enable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.NSTBE = 0b0
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* Trace Buffer owning Security state is Non-secure state. If FEAT_RME
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* is not implemented, this field is RES0.
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*
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* MDCR_EL3.NSTB = 0b11
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* Allow access of trace buffer control registers from NS-EL1 and
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* NS-EL2, tracing is prohibited in Secure and Realm state (if
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* implemented).
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*/
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mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL1);
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mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void trbe_disable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.{NSTBE,NSTB} = 0b0, 0b00
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* Disable access of trace buffer control registers from lower ELs in
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* any security state. Secure state owns the buffer.
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*/
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mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1));
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mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void trbe_init_el2_unused(void)
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{
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/*
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* MDCR_EL2.E2TB: Set to zero so that the trace Buffer
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* owning exception level is NS-EL1 and, tracing is
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* prohibited at NS-EL2. These bits are RES0 when
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* FEAT_TRBE is not implemented.
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*/
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write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
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}
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