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f4303d05ea
With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores can be handled. FEAT_TCR2 is one of the features which can be asymmetric across cores and the respective support is added here. Adding a function to handle this asymmetry by re-visting the feature presence on running core. There are two possible cases: - If the primary core has the feature and secondary does not have it then the feature is disabled. - If the primary does not have the feature and secondary has it then, the feature need to be enabled in secondary cores. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I73a70891d52268ddfa4effe40edf04115f5821ca
42 lines
860 B
C
42 lines
860 B
C
/*
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* Copyright (c) 2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/extensions/tcr2.h>
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void tcr2_enable(cpu_context_t *ctx)
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{
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u_register_t reg;
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el3_state_t *state;
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state = get_el3state_ctx(ctx);
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/* Set the TCR2EN bit in SCR_EL3 to enable access to TCR2_EL1,
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* and TCR2_EL2 registers .
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*/
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reg = read_ctx_reg(state, CTX_SCR_EL3);
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reg |= SCR_TCR2EN_BIT;
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write_ctx_reg(state, CTX_SCR_EL3, reg);
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}
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void tcr2_disable(cpu_context_t *ctx)
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{
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u_register_t reg;
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el3_state_t *state;
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state = get_el3state_ctx(ctx);
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/* Clear the TCR2EN bit in SCR_EL3 to disable access to TCR2_EL1,
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* and TCR2_EL2 registers .
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*/
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reg = read_ctx_reg(state, CTX_SCR_EL3);
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reg &= ~SCR_TCR2EN_BIT;
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write_ctx_reg(state, CTX_SCR_EL3, reg);
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}
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