mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00
58fadd62be
The following changes have been made: * Add new sysreg definitions and ASM macro is_feat_sysreg128_present_asm * Add registers TTBR0_EL2 and VTTBR_EL2 to EL3 crash handler output * Use MRRS instead of MRS for registers TTBR0_EL1, TTBR0_EL2, TTBR1_EL1, VTTBR_EL2 and PAR_EL1 Change-Id: I0e20b2c35251f3afba2df794c1f8bc0c46c197ff Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>
136 lines
3.1 KiB
ArmAsm
136 lines
3.1 KiB
ArmAsm
/*
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* Copyright (c) 2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <lib/extensions/sysreg128.h>
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.global read_par_el1
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.global write_par_el1
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.global read_ttbr0_el1
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.global write_ttbr0_el1
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.global read_ttbr1_el1
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.global write_ttbr1_el1
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.global read_ttbr0_el2
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.global write_ttbr0_el2
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.global read_ttbr1_el2
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.global write_ttbr1_el2
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.global read_vttbr_el2
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.global write_vttbr_el2
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.global read_rcwmask_el1
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.global write_rcwmask_el1
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.global read_rcwsmask_el1
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.global write_rcwsmask_el1
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/*
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* _mrrs - Move System register to two adjacent general-purpose
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* registers.
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* Instruction: MRRS <Xt>, <Xt+1>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)
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*
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* Arguments/Opcode bit field:
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* regins: System register opcode.
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*
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* Clobbers: x0,x1,x2
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*/
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.macro _mrrs regins:req
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#if ENABLE_FEAT_D128 == 2
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is_feat_sysreg128_present_asm x0
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bne 1f
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/* If FEAT_SYSREG128 is not implemented then use mrs */
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.inst 0xD5300000 | (\regins) /* mrs x0, \regins */
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ret
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#endif
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1:
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.inst 0xD5700000 | (\regins) /* mrrs x0, x1, \regins */
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ret
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.endm
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/*
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* _msrr - Move two adjacent general-purpose registers to System register.
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* Instruction: MSRR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>, <Xt+1>
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*
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* Arguments/Opcode bit field:
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* regins: System register opcode.
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*
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* Clobbers: x0,x1,x2
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*/
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.macro _msrr regins:req
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#if ENABLE_FEAT_D128 == 2
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/* Don't tamper x0 and x1 as they may be used for msrr */
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is_feat_sysreg128_present_asm x2
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bne 1f
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/* If FEAT_SYSREG128 is not implemented then use msr */
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.inst 0xD5100000 | (\regins) /* msr \regins, x0 */
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ret
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#endif
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1:
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.inst 0xD5500000 | (\regins) /* msrr \regins, x0, x1 */
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ret
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.endm
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func read_par_el1
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_mrrs 0x87400 /* S3_0_C7_C4_0 */
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endfunc read_par_el1
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func write_par_el1
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_msrr 0x87400
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endfunc write_par_el1
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func read_ttbr0_el1
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_mrrs 0x82000 /* S3_0_C2_C0_0 */
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endfunc read_ttbr0_el1
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func write_ttbr0_el1
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_msrr 0x82000
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endfunc write_ttbr0_el1
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func read_ttbr1_el1
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_mrrs 0x82020 /* S3_0_C2_C0_1 */
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endfunc read_ttbr1_el1
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func write_ttbr1_el1
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_msrr 0x82020
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endfunc write_ttbr1_el1
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func read_ttbr0_el2
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_mrrs 0xC2000 /* S3_4_C2_C0_0 */
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endfunc read_ttbr0_el2
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func write_ttbr0_el2
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_msrr 0xC2000
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endfunc write_ttbr0_el2
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func read_ttbr1_el2
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_mrrs 0xC2020 /* S3_4_C2_C0_1 */
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endfunc read_ttbr1_el2
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func write_ttbr1_el2
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_msrr 0xC2020
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endfunc write_ttbr1_el2
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func read_vttbr_el2
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_mrrs 0xC2100 /* S3_4_C2_C1_0 */
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endfunc read_vttbr_el2
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func write_vttbr_el2
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_msrr 0xC2100
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endfunc write_vttbr_el2
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func read_rcwmask_el1
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_mrrs 0x8D0C0 /* S3_0_C13_C0_6 */
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endfunc read_rcwmask_el1
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func write_rcwmask_el1
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_msrr 0x8D0C0
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endfunc write_rcwmask_el1
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func read_rcwsmask_el1
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_mrrs 0x8D060 /* S3_0_C13_C0_3 */
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endfunc read_rcwsmask_el1
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func write_rcwsmask_el1
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_msrr 0x8D060
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endfunc write_rcwsmask_el1
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