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461c0a5d92
Currently, EL3 context registers are duplicated per-world per-cpu. Some registers have the same value across all CPUs, so this patch moves these registers out into a per-world context to reduce memory usage. Change-Id: I91294e3d5f4af21a58c23599af2bdbd2a747c54a Signed-off-by: Elizabeth Ho <elizabeth.ho@arm.com> Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
45 lines
1.2 KiB
C
45 lines
1.2 KiB
C
/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/extensions/sys_reg_trace.h>
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void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx)
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{
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/*
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* CPTR_EL3.TTA: Set to zero so that System register accesses to the
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* trace registers do not trap to EL3.
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*/
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uint64_t val = per_world_ctx->ctx_cptr_el3;
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val &= ~(TTA_BIT);
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per_world_ctx->ctx_cptr_el3 = val;
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}
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void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx)
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{
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/*
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* CPTR_EL3.TTA: Set to one so that System register accesses to the
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* trace registers trap to EL3, unless it is trapped by CPACR.TRCDIS,
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* CPACR_EL1.TTA, or CPTR_EL2.TTA
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*/
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uint64_t val = per_world_ctx->ctx_cptr_el3;
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val |= TTA_BIT;
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per_world_ctx->ctx_cptr_el3 = val;
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}
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void sys_reg_trace_init_el2_unused(void)
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{
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/*
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* CPTR_EL2.TTA: Set to zero so that Non-secure System register accesses
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* to the trace registers from both Execution states do not trap to
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* EL2. If PE trace unit System registers are not implemented then this
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* bit is reserved, and must be set to zero.
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*/
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write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TTA_BIT);
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}
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