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https://github.com/ARM-software/arm-trusted-firmware.git
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e6f8fc7437
While comments introduced with the original commit claim that
pmuv3_disable_el3()/pmuv3_init_el3() are compatible with PMUv2 and
PMUv1, this is not true in practice: The function accesses the Secure
Debug Control Register (SDCR), which only available to ARMv8 CPUs.
ARMv8 CPUs executing in AArch32 mode would thus be able to disable
their PMUv3, while ARMv7 CPUs would hang trying to access the SDCR.
Fix this by only doing PMUv3 handling when we know a PMUv3 to be
available. This resolves boot hanging on all STM32MP15 platforms
that use SP_min as BL32 instead of OP-TEE.
Change-Id: I40f7611cf46b89a30243cc55bf55a8d9c9de93c8
Fixes: c73686a11c ("feat(pmu): introduce pmuv3 lib/extensions folder")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
68 lines
2 KiB
C
68 lines
2 KiB
C
/*
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* Copyright (c) 2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/extensions/pmuv3.h>
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static u_register_t mtpmu_disable_el3(u_register_t sdcr)
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{
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if (!is_feat_mtpmu_supported()) {
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return sdcr;
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}
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/*
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* SDCR.MTPME = 0
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* FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>.MT is
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* zero.
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*/
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sdcr &= ~SDCR_MTPME_BIT;
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return sdcr;
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}
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void pmuv3_init_el3(void)
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{
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u_register_t sdcr = read_sdcr();
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/* ---------------------------------------------------------------------
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* Initialise SDCR, setting all the fields rather than relying on hw.
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*
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* SDCR.SCCD: Set to one so that cycle counting by PMCCNTR is prohibited
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* in Secure state. This bit is RES0 in versions of the architecture
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* earlier than ARMv8.5
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*
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* SDCR.SPME: Set to zero so that event counting is prohibited in Secure
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* state (and explicitly EL3 with later revisions). If ARMv8.2 Debug is
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* not implemented this bit does not have any effect on the counters
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* unless there is support for the implementation defined
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* authentication interface ExternalSecureNoninvasiveDebugEnabled().
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* ---------------------------------------------------------------------
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*/
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sdcr = (sdcr | SDCR_SCCD_BIT) & ~SDCR_SPME_BIT;
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sdcr = mtpmu_disable_el3(sdcr);
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write_sdcr(sdcr);
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/* ---------------------------------------------------------------------
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* Initialise PMCR, setting all fields rather than relying
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* on hw. Some fields are architecturally UNKNOWN on reset.
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*
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* PMCR.DP: Set to one to prohibit cycle counting whilst in Secure mode.
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*
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* PMCR.X: Set to zero to disable export of events.
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*
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* PMCR.C: Set to one to reset PMCCNTR.
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*
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* PMCR.P: Set to one to reset each event counter PMEVCNTR<n> to zero.
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*
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* PMCR.E: Set to zero to disable cycle and event counters.
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* ---------------------------------------------------------------------
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*/
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write_pmcr(read_pmcr() | PMCR_DP_BIT | PMCR_C_BIT | PMCR_P_BIT |
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~(PMCR_X_BIT | PMCR_E_BIT));
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}
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