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https://github.com/ARM-software/arm-trusted-firmware.git
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94127ae299
Retrieve DLME image authentication features and report them back to the DCE preamble. Currently, this value is always set to 0, as no platform supports DLME authentication. Additionally, the default schema is always used instead of the DLME PCR schema since DLME authentication is not currently supported. This change primarily upgrades the DRTM parameters version to V2, aligning with DRTM spec v1.1 [1]. [1]: https://developer.arm.com/documentation/den0113/c/?lang=en Change-Id: Ie2ceb0d2ff49465643597e8725710a93d89e74a2 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
255 lines
9.3 KiB
C
255 lines
9.3 KiB
C
/*
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* Copyright (c) 2022-2025 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* DRTM service
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*
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* Authors:
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* Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
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* Brian Nezvadovitz <brinez@microsoft.com> 2021-02-01
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*
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*/
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#ifndef ARM_DRTM_SVC_H
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#define ARM_DRTM_SVC_H
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/*
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* SMC function IDs for DRTM Service
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* Upper word bits set: Fast call, SMC64, Standard Secure Svc. Call (OEN = 4)
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*/
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#define DRTM_FID(func_num) \
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((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \
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(SMC_64 << FUNCID_CC_SHIFT) | \
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(OEN_STD_START << FUNCID_OEN_SHIFT) | \
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((func_num) << FUNCID_NUM_SHIFT))
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#define DRTM_FNUM_SVC_VERSION U(0x110)
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#define DRTM_FNUM_SVC_FEATURES U(0x111)
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#define DRTM_FNUM_SVC_UNPROTECT_MEM U(0x113)
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#define DRTM_FNUM_SVC_DYNAMIC_LAUNCH U(0x114)
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#define DRTM_FNUM_SVC_CLOSE_LOCALITY U(0x115)
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#define DRTM_FNUM_SVC_GET_ERROR U(0x116)
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#define DRTM_FNUM_SVC_SET_ERROR U(0x117)
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#define DRTM_FNUM_SVC_SET_TCB_HASH U(0x118)
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#define DRTM_FNUM_SVC_LOCK_TCB_HASH U(0x119)
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#define ARM_DRTM_SVC_VERSION DRTM_FID(DRTM_FNUM_SVC_VERSION)
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#define ARM_DRTM_SVC_FEATURES DRTM_FID(DRTM_FNUM_SVC_FEATURES)
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#define ARM_DRTM_SVC_UNPROTECT_MEM DRTM_FID(DRTM_FNUM_SVC_UNPROTECT_MEM)
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#define ARM_DRTM_SVC_DYNAMIC_LAUNCH DRTM_FID(DRTM_FNUM_SVC_DYNAMIC_LAUNCH)
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#define ARM_DRTM_SVC_CLOSE_LOCALITY DRTM_FID(DRTM_FNUM_SVC_CLOSE_LOCALITY)
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#define ARM_DRTM_SVC_GET_ERROR DRTM_FID(DRTM_FNUM_SVC_GET_ERROR)
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#define ARM_DRTM_SVC_SET_ERROR DRTM_FID(DRTM_FNUM_SVC_SET_ERROR)
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#define ARM_DRTM_SVC_SET_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_SET_TCB_HASH)
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#define ARM_DRTM_SVC_LOCK_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_LOCK_TCB_HASH)
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#define ARM_DRTM_FEATURES_TPM U(0x1)
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#define ARM_DRTM_FEATURES_MEM_REQ U(0x2)
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#define ARM_DRTM_FEATURES_DMA_PROT U(0x3)
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#define ARM_DRTM_FEATURES_BOOT_PE_ID U(0x4)
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#define ARM_DRTM_FEATURES_TCB_HASHES U(0x5)
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#define ARM_DRTM_FEATURES_DLME_IMG_AUTH U(0x6)
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#define is_drtm_fid(_fid) \
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(((_fid) >= ARM_DRTM_SVC_VERSION) && ((_fid) <= ARM_DRTM_SVC_LOCK_TCB_HASH))
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/* ARM DRTM Service Calls version numbers */
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#define ARM_DRTM_VERSION_MAJOR U(1)
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#define ARM_DRTM_VERSION_MAJOR_SHIFT 16
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#define ARM_DRTM_VERSION_MAJOR_MASK U(0x7FFF)
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#define ARM_DRTM_VERSION_MINOR U(0)
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#define ARM_DRTM_VERSION_MINOR_SHIFT 0
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#define ARM_DRTM_VERSION_MINOR_MASK U(0xFFFF)
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#define ARM_DRTM_VERSION \
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((((ARM_DRTM_VERSION_MAJOR) & ARM_DRTM_VERSION_MAJOR_MASK) << \
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ARM_DRTM_VERSION_MAJOR_SHIFT) \
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| (((ARM_DRTM_VERSION_MINOR) & ARM_DRTM_VERSION_MINOR_MASK) << \
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ARM_DRTM_VERSION_MINOR_SHIFT))
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#define ARM_DRTM_FUNC_SHIFT U(63)
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#define ARM_DRTM_FUNC_MASK ULL(0x1)
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#define ARM_DRTM_FUNC_ID U(0x0)
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#define ARM_DRTM_FEAT_ID U(0x1)
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#define ARM_DRTM_FEAT_ID_MASK ULL(0xff)
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/*
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* Definitions for DRTM features as per DRTM 1.0 section 3.3,
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* Table 6 DRTM_FEATURES
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*/
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#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT U(33)
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#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK ULL(0xF)
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#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT ULL(0x1)
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#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT U(32)
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#define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK ULL(0x1)
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#define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED ULL(0x0)
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#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED ULL(0x1)
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#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT U(0)
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#define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK ULL(0xFFFF)
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#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256 ULL(0xB)
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#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384 ULL(0xC)
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#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512 ULL(0xD)
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#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT U(32)
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#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK ULL(0xFFFFFFFF)
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#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT U(0)
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#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF)
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#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT U(8)
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#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF)
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#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT U(0)
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#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF)
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#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE ULL(0x1)
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#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION ULL(0x2)
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#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT U(0)
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#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK ULL(0xFF)
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#define ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT U(0)
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#define ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK ULL(0x1)
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#define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \
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do { \
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reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \
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<< ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \
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ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK) << \
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ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)); \
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} while (false)
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#define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val) \
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do { \
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reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK \
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<< ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) & \
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ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK) << \
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ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)); \
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} while (false)
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#define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val) \
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do { \
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reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK \
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<< ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) & \
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ARM_DRTM_TPM_FEATURES_FW_HASH_MASK) << \
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ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)); \
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} while (false)
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#define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val) \
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do { \
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reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK \
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<< ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) & \
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ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK) << \
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ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)); \
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} while (false)
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#define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val) \
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do { \
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reg = (((reg) & \
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~(ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK << \
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ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)) | \
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(((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \
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<< ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)); \
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} while (false)
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#define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val) \
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do { \
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reg = (((reg) & \
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~(ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK << \
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ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)) | \
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(((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK) \
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<< ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)); \
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} while (false)
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#define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \
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do { \
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reg = (((reg) & \
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~(ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK << \
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ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)) | \
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(((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK) \
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<< ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)); \
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} while (false)
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#define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val) \
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do { \
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reg = (((reg) & \
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~(ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK << \
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ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)) | \
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(((val) & \
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ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK) << \
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ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)); \
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} while (false)
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#define ARM_DRTM_DLME_IMG_AUTH_SUPPORT(reg, val) \
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do { \
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reg = (((reg) & \
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~(ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK << \
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ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT)) | \
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(((val) & \
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ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK) << \
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ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT)); \
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} while (false)
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/* Definitions for DRTM address map */
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#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT U(55)
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#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK ULL(0x3)
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#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC ULL(0)
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#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC ULL(1)
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#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT ULL(2)
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#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB ULL(3)
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#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT U(52)
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#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK ULL(0x7)
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#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL ULL(0)
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#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR ULL(1)
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#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE ULL(2)
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#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV ULL(3)
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#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD ULL(4)
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#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT U(0)
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#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK ULL(0xFFFFFFFFFFFFF)
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#define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val) \
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do { \
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reg = (((reg) & \
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~(ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK << \
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ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)) | \
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(((val) & \
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ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK) << \
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ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)); \
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} while (false)
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#define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val) \
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do { \
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reg = (((reg) & \
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~(ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK << \
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ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)) | \
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(((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK) \
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<< ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)); \
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} while (false)
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#define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val) \
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do { \
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reg = (((reg) & \
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~(ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK << \
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ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)) | \
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(((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK) \
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<< ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)); \
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} while (false)
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/* Initialization routine for the DRTM service */
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int drtm_setup(void);
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/* Handler to be called to handle DRTM SMC calls */
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uint64_t drtm_smc_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags);
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#endif /* ARM_DRTM_SVC_H */
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