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https://github.com/ARM-software/arm-trusted-firmware.git
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cea55c836f
Enable the Arm SPE DT binding for TC4. Signed-off-by: Leo Yan <leo.yan@arm.com> Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com> Change-Id: I9ea49046a663eecc2b97ecef9ca939575d71fdd9
157 lines
3.2 KiB
Text
157 lines
3.2 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <platform_def.h>
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#define MHU_TX_ADDR 46240000 /* hex */
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#define MHU_RX_ADDR 46250000 /* hex */
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#define LIT_CPU_PMU_COMPATIBLE "arm,nevis-pmu"
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#define MID_CPU_PMU_COMPATIBLE "arm,gelas-pmu"
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#define BIG_CPU_PMU_COMPATIBLE "arm,travis-pmu"
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#define RSE_MHU_TX_ADDR 49020000 /* hex */
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#define RSE_MHU_RX_ADDR 49030000 /* hex */
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#if TARGET_FLAVOUR_FVP
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#define ETHERNET_ADDR 64000000
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#define ETHERNET_INT 799
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#define SYS_REGS_ADDR 60080000
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#define MMC_ADDR 600b0000
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#define MMC_INT_0 778
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#define MMC_INT_1 779
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#else /* TARGET_FLAVOUR_FPGA */
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#define ETHERNET_ADDR 18000000
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#define ETHERNET_INT 109
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#define SYS_REGS_ADDR 1c010000
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#define MMC_ADDR 1c050000
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#define MMC_INT_0 107
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#define MMC_INT_1 108
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#endif /* TARGET_FLAVOUR_FVP */
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#define RTC_ADDR 600a0000
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#define RTC_INT 777
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#define KMI_0_ADDR 60100000
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#define KMI_0_INT 784
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#define KMI_1_ADDR 60110000
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#define KMI_1_INT 785
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#define VIRTIO_BLOCK_ADDR 60020000
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#define VIRTIO_BLOCK_INT 769
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#if TARGET_FLAVOUR_FPGA
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#define DPU_ADDR 4000000000
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#define DPU_IRQ 579
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#endif
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#include "tc-common.dtsi"
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#if TARGET_FLAVOUR_FVP
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#include "tc-fvp.dtsi"
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#else
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#include "tc-fpga.dtsi"
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#endif /* TARGET_FLAVOUR_FVP */
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#include "tc3-4-base.dtsi"
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/ {
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spe-pmu-mid {
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status = "okay";
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};
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spe-pmu-big {
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status = "okay";
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};
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smmu_700: iommu@3f000000 {
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status = "okay";
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};
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smmu_700_dpu: iommu@4002a00000 {
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status = "okay";
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};
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dp0: display@DPU_ADDR {
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iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
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<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
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};
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gpu: gpu@2d000000 {
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interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "IRQAW";
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iommus = <&smmu_700 0x0>;
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system-coherency = <0x0>;
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};
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dsu-pmu {
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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cs-pmu@4 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(4) 0x0 0xffc>;
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};
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cs-pmu@5 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(5) 0x0 0xffc>;
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};
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cs-pmu@6 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(6) 0x0 0xffc>;
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};
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cs-pmu@7 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>;
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};
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#if defined(TARGET_FLAVOUR_FPGA)
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slc-msc@0 {
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compatible = "arm,mpam-msc";
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reg = <0x0 MCN_MPAM_NS_BASE_ADDR(0) 0x0 0x4000>;
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};
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slc-msc@1 {
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compatible = "arm,mpam-msc";
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reg = <0x0 MCN_MPAM_NS_BASE_ADDR(1) 0x0 0x4000>;
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};
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slc-msc@2 {
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compatible = "arm,mpam-msc";
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reg = <0x0 MCN_MPAM_NS_BASE_ADDR(2) 0x0 0x4000>;
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};
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slc-msc@3 {
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compatible = "arm,mpam-msc";
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reg = <0x0 MCN_MPAM_NS_BASE_ADDR(3) 0x0 0x4000>;
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};
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slc-msc@4 {
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compatible = "arm,mpam-msc";
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reg = <0x0 MCN_MPAM_NS_BASE_ADDR(4) 0x0 0x4000>;
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};
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slc-msc@5 {
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compatible = "arm,mpam-msc";
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reg = <0x0 MCN_MPAM_NS_BASE_ADDR(5) 0x0 0x4000>;
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};
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slc-msc@6 {
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compatible = "arm,mpam-msc";
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reg = <0x0 MCN_MPAM_NS_BASE_ADDR(6) 0x0 0x4000>;
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};
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slc-msc@7 {
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compatible = "arm,mpam-msc";
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reg = <0x0 MCN_MPAM_NS_BASE_ADDR(7) 0x0 0x4000>;
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};
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#endif /* TARGET_FLAVOUR_FPGA */
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};
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