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https://github.com/ARM-software/arm-trusted-firmware.git
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1d2d96dd5c
The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")
To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.
We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d
84 lines
2 KiB
Text
84 lines
2 KiB
Text
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define GIC_CTRL_ADDR 2c010000
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#define GIC_GICR_OFFSET 0x200000
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#define UART_OFFSET 0x1000
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#ifdef TC_RESOLUTION_1920X1080P60
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#define LCD_TIMING_CLK 148500000
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#define LCD_TIMING \
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clock-frequency = <LCD_TIMING_CLK>; \
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hactive = <1920>; \
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vactive = <1080>; \
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hfront-porch = <88>; \
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hback-porch = <148>; \
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hsync-len = <44>; \
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vfront-porch = <4>; \
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vback-porch = <36>; \
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vsync-len = <5>
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#else /* TC_RESOLUTION_640X480P60 */
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#define LCD_TIMING_CLK 25175000
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#define LCD_TIMING \
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clock-frequency = <LCD_TIMING_CLK>; \
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hactive = <640>; \
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vactive = <480>; \
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hfront-porch = <16>; \
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hback-porch = <48>; \
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hsync-len = <96>; \
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vfront-porch = <10>; \
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vback-porch = <33>; \
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vsync-len = <2>
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#endif
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/ {
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chosen {
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stdout-path = "serial0:115200n8";
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};
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ethernet: ethernet@ETHERNET_ADDR {
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compatible = "smsc,lan91c111";
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};
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mmci: mmci@MMC_ADDR {
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cd-gpios = <&sysreg 0 0>;
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};
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rtc@RTC_ADDR {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x0 ADDRESSIFY(RTC_ADDR) 0x0 0x1000>;
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interrupts = <GIC_SPI RTC_INT IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&soc_refclk>;
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clock-names = "apb_pclk";
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};
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kmi@KMI_0_ADDR {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 ADDRESSIFY(KMI_0_ADDR) 0x0 0x1000>;
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interrupts = <GIC_SPI KMI_0_INT IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c070000 0x0 0x1000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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virtio_block@VIRTIO_BLOCK_ADDR {
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compatible = "virtio,mmio";
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reg = <0x0 ADDRESSIFY(VIRTIO_BLOCK_ADDR) 0x0 0x200>;
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/* spec lists this wrong */
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interrupts = <GIC_SPI VIRTIO_BLOCK_INT IRQ_TYPE_LEVEL_HIGH 0>;
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};
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};
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