mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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6a9e5ffda7
Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC, with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ... Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Olivier BIDEAU <olivier.bideau@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I95bb84b00eafce8031f26f7243ecc0fce843d170
97 lines
1.9 KiB
Text
97 lines
1.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
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* Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics.
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*/
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/*
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* STM32MP25 Clock tree device tree configuration
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* Project : open
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* Generated by XLmx tool version 2.2 - 3/6/2024 11:20:07 AM
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*/
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&clk_hse {
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clock-frequency = <40000000>;
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};
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&clk_hsi {
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clock-frequency = <64000000>;
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};
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&clk_lse {
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clock-frequency = <32768>;
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};
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&clk_lsi {
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clock-frequency = <32000>;
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};
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&clk_msi {
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clock-frequency = <16000000>;
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};
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&rcc {
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st,busclk = <
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DIV_CFG(DIV_LSMCU, 1)
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DIV_CFG(DIV_APB1, 0)
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DIV_CFG(DIV_APB2, 0)
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DIV_CFG(DIV_APB3, 0)
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DIV_CFG(DIV_APB4, 0)
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DIV_CFG(DIV_APBDBG, 0)
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>;
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st,flexgen = <
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FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
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FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
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FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
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FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
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FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
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FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0)
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FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
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FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
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FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
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FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1)
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FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
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>;
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st,kerclk = <
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MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
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MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
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>;
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pll1: st,pll-1 {
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st,pll = <&pll1_cfg_1200Mhz>;
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pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
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cfg = <30 1 1 1>;
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src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
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};
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};
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pll2: st,pll-2 {
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st,pll = <&pll2_cfg_600Mhz>;
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pll2_cfg_600Mhz: pll2-cfg-600Mhz {
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cfg = <30 1 1 2>;
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src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
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};
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};
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pll4: st,pll-4 {
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st,pll = <&pll4_cfg_1200Mhz>;
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pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
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cfg = <30 1 1 1>;
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src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
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};
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};
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pll5: st,pll-5 {
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st,pll = <&pll5_cfg_532Mhz>;
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pll5_cfg_532Mhz: pll5-cfg-532Mhz {
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cfg = <133 5 1 2>;
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src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
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};
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};
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};
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