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2974d2f2d0
If not mentioned explicitly, numa-node-id for pcie_ctlr is assigned as unknown. With this patch pcie_ctlr and ccix_pcie_ctlr are assigned numa-node-id=0 and pcie_secondary_ctlr is assigned numa-node-id=1. Signed-off-by: sahil <sahil@arm.com> Change-Id: I533abdd6ea162df7b15ee04cbfc48ba7a544b91a
122 lines
2.9 KiB
Text
122 lines
2.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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* Copyright (c) 2019-2022, Arm Limited.
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*/
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#include "n1sdp-single-chip.dts"
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/ {
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cpus {
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cpu4@100000000 {
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compatible = "arm,neoverse-n1";
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reg = <0x1 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <1>;
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};
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cpu5@100000100 {
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compatible = "arm,neoverse-n1";
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reg = <0x1 0x00000100>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <1>;
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};
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cpu6@100010000 {
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compatible = "arm,neoverse-n1";
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reg = <0x1 0x00010000>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <1>;
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};
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cpu7@100010100 {
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compatible = "arm,neoverse-n1";
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reg = <0x1 0x00010100>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <1>;
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};
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};
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/* Remote N1SDP board address is mapped at offset 4TB.
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* First DRAM Bank of remote N1SDP board is mapped at 4TB + 2GB.
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*/
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memory@40080000000 {
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device_type = "memory";
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reg = <0x00000400 0x80000000 0x0 0x80000000>,
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<0x00000480 0x80000000 0x3 0x80000000>;
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numa-node-id = <1>;
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};
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distance-map {
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compatible = "numa-distance-map-v1";
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distance-matrix = <0 0 10>,
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<0 1 20>,
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<1 1 10>;
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};
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smmu_secondary_pcie: iommu@4004f400000 {
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compatible = "arm,smmu-v3";
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reg = <0x400 0x4f400000 0 0x40000>;
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interrupts = <GIC_SPI 715 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 716 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 717 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "cmdq-sync", "gerror";
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msi-parent = <&its2_secondary 0>;
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#iommu-cells = <1>;
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dma-coherent;
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};
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pcie_secondary_ctlr: pcie@40070000000 {
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compatible = "arm,n1sdp-pcie";
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device_type = "pci";
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reg = <0x400 0x70000000 0 0x1200000>;
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bus-range = <0 0xff>;
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linux,pci-domain = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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dma-coherent;
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ranges = <0x01000000 0x00 0x00000000 0x400 0x75200000 0x00 0x00010000>,
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<0x02000000 0x00 0x71200000 0x400 0x71200000 0x00 0x04000000>,
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<0x42000000 0x09 0x00000000 0x409 0x00000000 0x20 0x00000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic 0 0 0 649 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gic 0 0 0 650 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gic 0 0 0 651 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gic 0 0 0 652 IRQ_TYPE_LEVEL_HIGH>;
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msi-map = <0 &its_secondary_pcie 0 0x10000>;
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iommu-map = <0 &smmu_secondary_pcie 0 0x10000>;
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numa-node-id = <1>;
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status = "okay";
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};
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};
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&gic {
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#redistributor-regions = <2>;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x300c0000 0 0x80000>, /* GICR */
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<0x400 0x300c0000 0 0x80000>; /* GICR */
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its2_secondary: its@40030060000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x400 0x30060000 0x0 0x20000>;
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};
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its_secondary_pcie: its@400300a0000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x400 0x300a0000 0x0 0x20000>;
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};
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};
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&pcie_ctlr {
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numa-node-id = <0>;
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};
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&ccix_pcie_ctlr {
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numa-node-id = <0>;
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};
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