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https://github.com/ARM-software/arm-trusted-firmware.git
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2716bd33e3
The existing DT files for the base FVP model are having some issues, that lead to warnings reported by the device tree compiler. Those (and many other issues around (updated) DT binding compliance) were fixed in the Linux kernel tree, so let's sync those files back into TF-A. We cannot copy the files "as is" for now, since we rely on certain custom properties to be added (max-pwr-lvl in the PSCI node, SDEI nodes, etc). Merge in the changed parts of the Linux kernel DT (from Linux v6.0-rc1), and rework the base file to allow including the motherboard.dtsi unchanged. This should make any future update less painful. As this also affects the FVP VE boards (Cortex-A7 and Cortex-A5), since they share the motherboard include file, fix them up as well. Change-Id: I4f74d05e5583747f8849e32f246f74aeec7a9c60 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
102 lines
2.5 KiB
Text
102 lines
2.5 KiB
Text
/*
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* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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#include "rtsm_ve-motherboard.dtsi"
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/ {
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model = "V2F-1XV7 Cortex-A7x1 SMM";
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compatible = "arm,vexpress,v2f-1xv7", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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};
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};
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memory@0,80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0x80000000>; /* 2GB @ 2GB */
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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/* Chipselect 2,00000000 is physically at 0x18000000 */
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vram: vram@18000000 {
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/* 8 MB of designated video RAM */
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compatible = "shared-dma-pool";
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reg = <0 0x18000000 0x00800000>;
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no-map;
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};
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0x1000>,
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<0 0x2c002000 0x1000>,
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<0 0x2c004000 0x2000>,
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<0 0x2c006000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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smbclk: refclk24mhzx2 {
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/* Reference 24MHz clock x 2 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "smclk";
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};
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panel {
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compatible = "arm,rtsm-display";
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port {
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panel_in: endpoint {
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remote-endpoint = <&clcd_pads>;
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};
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};
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};
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bus@8000000 {
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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