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https://github.com/ARM-software/arm-trusted-firmware.git
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ddaf02d171
This patch is used to implement sdmmc/nand/combo-phy driver to support Cadence IP for Agilex5 SoC FPGA. 1. Added SDMMC/NAND/COMBO-PHY support. 2. Updated product name -> Agilex5 3. Updated QSPI base address Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
83 lines
2 KiB
C
83 lines
2 KiB
C
/*
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* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/cadence/cdns_combo_phy.h>
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#include <drivers/cadence/cdns_sdmmc.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value,
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uint32_t phy_reg_data, uint32_t phy_reg_data_value)
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{
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uint32_t data = 0U;
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uint32_t value = 0U;
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/* Get PHY register address, write HRS04*/
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value = mmio_read_32(phy_reg_addr);
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value &= ~PHY_REG_ADDR_MASK;
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value |= phy_reg_addr_value;
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mmio_write_32(phy_reg_addr, value);
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data = mmio_read_32(phy_reg_addr);
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if ((data & PHY_REG_ADDR_MASK) != phy_reg_addr_value) {
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ERROR("PHY_REG_ADDR is not set properly\n");
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return -ENXIO;
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}
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/* Get PHY register data, write HRS05 */
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value &= ~PHY_REG_DATA_MASK;
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value |= phy_reg_data_value;
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mmio_write_32(phy_reg_data, value);
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data = mmio_read_32(phy_reg_data);
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if (data != phy_reg_data_value) {
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ERROR("PHY_REG_DATA is not set properly\n");
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return -ENXIO;
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}
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return 0;
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}
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int cdns_sd_card_detect(void)
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{
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uint32_t value = 0;
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/* Card detection */
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do {
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value = mmio_read_32(SDMMC_CDN(SRS09));
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/* Wait for card insertion. SRS09.CI = 1 */
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} while ((value & (1 << SDMMC_CDN_CI)) == 0);
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if ((value & (1 << SDMMC_CDN_CI)) == 0) {
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ERROR("Card does not detect\n");
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return -ENXIO;
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}
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return 0;
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}
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int cdns_emmc_card_reset(void)
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{
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uint32_t _status = 0;
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/* Reset embedded card */
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mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status);
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mdelay(68680); /* ~68680us */
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mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP));
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udelay(340); /* ~340us */
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/* Turn on supply voltage */
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/* BVS = 7, BP = 1, BP2 only in UHS2 mode */
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mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status);
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return 0;
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}
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