Maxime Méré ae84525f44 feat(stm32mp2): manage DDR FW via FIP ... This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE. DDR firmware binary is loaded from FIP to SRAM1 which needs to be mapped. Only half of the SRAM1 will be allocated to TF-A. RISAB3 has to be configured to allow access to SRAM1. Add image ID and update maximum number on platform side also. Fill related descriptor information, add policy and update numbers. DDR_TYPE variable is used to identify binary file, and image is now added in the fiptool command line. The DDR PHY firmware is not in TF-A repository. It can be found at https://github.com/STMicroelectronics/stm32-ddr-phy-binary To ease the selection of the firmware path, STM32MP_DDR_FW_PATH is added to platform.mk file. Change-Id: I09ab0a5c63406055a7b5ccd16d65e443de47ca2f Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>		2024-09-13 17:57:58 +02:00
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index.rst	feat(docs): introduce STM32MP2 doc	2023-09-08 10:56:49 +02:00
stm32mp1.rst	docs(st): set OP-TEE as default BL32	2024-03-19 11:02:24 +01:00
stm32mp2.rst	feat(stm32mp2): manage DDR FW via FIP	2024-09-13 17:57:58 +02:00
stm32mpus.rst	refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE	2024-04-24 15:44:28 +02:00