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564e073cd5
Revise the AST2700 boot flow to the RESET_TO_BL31 scheme. The execution of BL1/2 can be saved from ARM CA35 while most low level platform initialization are moved to a preceding MCU. This patch updates the build configuration and also adds the SMP mailbox setup code to hold secondary cores until they are being waken up. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Change-Id: I7e0aa6416b92b97036153db1d9a26baaa41b7b18
17 lines
326 B
ReStructuredText
17 lines
326 B
ReStructuredText
Aspeed AST2700
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Aspeed AST2700 is a 64-bit ARM SoC with 4-cores Cortex-A35 integrated.
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Each core operates at 1.6GHz.
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Boot Flow
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---------
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BootRom --> TF-A BL31 --> BL32 --> BL33 --> Linux Kernel
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How to build
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------------
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.. code:: shell
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=ast2700 SPD=opteed
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