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MPMM is a core-specific microarchitectural feature. It has been present in every Arm core since the Cortex-A510 and has been implemented in exactly the same way. Despite that, it is enabled more like an architectural feature with a top level enable flag. This utilised the identical implementation. This duality has left MPMM in an awkward place, where its enablement should be generic, like an architectural feature, but since it is not, it should also be core-specific if it ever changes. One choice to do this has been through the device tree. This has worked just fine so far, however, recent implementations expose a weakness in that this is rather slow - the device tree has to be read, there's a long call stack of functions with many branches, and system registers are read. In the hot path of PSCI CPU powerdown, this has a significant and measurable impact. Besides it being a rather large amount of code that is difficult to understand. Since MPMM is a microarchitectural feature, its correct placement is in the reset function. The essence of the current enablement is to write CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C enablement with an assembly macro in each CPU's reset function achieves the same effect with just a single close branch and a grand total of 6 instructions (versus the old 2 branches and 32 instructions). Having done this, the device tree entry becomes redundant. Should a core that doesn't support MPMM arise, this can cleanly be handled in the reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks mechanisms become obsolete and are removed. Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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Maximum Power Mitigation Mechanism (MPMM)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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|MPMM| is an optional microarchitectural power management mechanism supported by
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some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and
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Cortex-A510 cores. This mechanism detects and limits high-activity events to
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assist in |SoC| processor power domain dynamic power budgeting and limit the
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triggering of whole-rail (i.e. clock chopping) responses to overcurrent
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conditions.
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|MPMM| is enabled on a per-core basis by the EL3 runtime firmware.
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.. warning::
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|MPMM| exposes gear metrics through the auxiliary |AMU| counters. An
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external power controller can use these metrics to budget SoC power by
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limiting the number of cores that can execute higher-activity workloads or
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switching to a different DVFS operating point. When this is the case, the
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|AMU| counters that make up the |MPMM| gears must be enabled by the EL3
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runtime firmware - please see :ref:`Activity Monitor Auxiliary Counters` for
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documentation on enabling auxiliary |AMU| counters.
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