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https://github.com/ARM-software/arm-trusted-firmware.git
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9f98aa1a7e
At present, the entry point for each BL image is specified via the Makefiles and provided on the command line to the linker. When using a link script the entry point should rather be specified via the ENTRY() directive in the link script. This patch updates linker scripts of all BL images to specify the entry point using the ENTRY() directive. It also removes the --entry flag passed to the linker through Makefile. Fixes issue ARM-software/tf-issues#66 Change-Id: I1369493ebbacea31885b51185441f6b628cf8da0
158 lines
5.3 KiB
ArmAsm
158 lines
5.3 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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.globl bl1_entrypoint
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.section .text, "ax"; .align 3
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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bl1_entrypoint: ; .type bl1_entrypoint, %function
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/* ---------------------------------------------
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* Perform any processor specific actions upon
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* reset e.g. cache, tlb invalidations etc.
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* ---------------------------------------------
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*/
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bl cpu_reset_handler
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, early_exceptions
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msr vbar_el3, x0
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* Reserved and should not be modified.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* ---------------------------------------------------------------------
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*/
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mrs x0, cptr_el3
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bic w0, w0, #TCPAC_BIT
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bic w0, w0, #TTA_BIT
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bic w0, w0, #TFP_BIT
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msr cptr_el3, x0
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/* ---------------------------------------------
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* Enable the instruction cache.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el3
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orr x0, x0, #SCTLR_I_BIT
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msr sctlr_el3, x0
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isb
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_wait_for_entrypoint:
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/* ---------------------------------------------
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* Find the type of reset and jump to handler
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* if present. If the handler is null then it is
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* a cold boot. The primary cpu will set up the
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* platform while the secondaries wait for
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* their turn to be woken up
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* ---------------------------------------------
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*/
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bl read_mpidr
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bl platform_get_entrypoint
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cbnz x0, _do_warm_boot
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bl read_mpidr
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bl platform_is_primary_cpu
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cbnz x0, _do_cold_boot
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/* ---------------------------------------------
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* Perform any platform specific secondary cpu
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* actions
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* ---------------------------------------------
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*/
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bl plat_secondary_cold_boot_setup
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b _wait_for_entrypoint
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_do_cold_boot:
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/* ---------------------------------------------
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* Init C runtime environment.
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* - Zero-initialise the NOBITS sections.
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* There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* - Copy the data section from BL1 image
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* (stored in ROM) to the correct location
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* in RAM.
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* ---------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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ldr x0, =__DATA_RAM_START__
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ldr x1, =__DATA_ROM_START__
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ldr x2, =__DATA_SIZE__
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bl memcpy16
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/* ---------------------------------------------
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* Initialize platform and jump to our c-entry
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* point for this type of reset
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* ---------------------------------------------
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*/
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adr x0, bl1_main
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bl platform_cold_boot_init
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b _panic
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_do_warm_boot:
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/* ---------------------------------------------
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* Jump to BL31 for all warm boot init.
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* ---------------------------------------------
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*/
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blr x0
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_panic:
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b _panic
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