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https://github.com/ARM-software/arm-trusted-firmware.git
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9e86490f8f
BL3-1 architecture setup code programs the system counter frequency into the CNTFRQ_EL0 register. This frequency is defined by the platform, though. This patch introduces a new platform hook that the architecture setup code can call to retrieve this information. In the ARM FVP port, this returns the first entry of the frequency modes table from the memory mapped generic timer. All system counter setup code has been removed from BL1 as some platforms may not have initialized the system counters at this stage. The platform specific settings done exclusively in BL1 have been moved to BL3-1. In the ARM FVP port, this consists in enabling and initializing the System level generic timer. Also, the frequency change request in the counter control register has been set to 0 to make it explicit it's using the base frequency. The CNTCR_FCREQ() macro has been fixed in this context to give an entry number rather than a bitmask. In future, when support for firmware update is implemented, there is a case where BL1 platform specific code will need to program the counter frequency. This should be implemented at that time. This patch also updates the relevant documentation. It properly fixes ARM-software/tf-issues#24 Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
104 lines
3.8 KiB
C
104 lines
3.8 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <platform.h>
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#include <assert.h>
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/*******************************************************************************
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* This duplicates what the primary cpu did after a cold boot in BL1. The same
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* needs to be done when a cpu is hotplugged in. This function could also over-
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* ride any EL3 setup done by BL1 as this code resides in rw memory.
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******************************************************************************/
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void bl31_arch_setup(void)
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{
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unsigned long tmp_reg = 0;
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uint64_t counter_freq;
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/* Enable alignment checks and set the exception endianness to LE */
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tmp_reg = read_sctlr_el3();
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tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT);
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tmp_reg &= ~SCTLR_EE_BIT;
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write_sctlr_el3(tmp_reg);
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/*
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* Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route
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* external abort and SError interrupts to EL3
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*/
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tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT |
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SCR_FIQ_BIT;
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write_scr(tmp_reg);
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/*
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* Enable SError and Debug exceptions
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*/
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enable_serror();
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enable_debug_exceptions();
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/* Program the counter frequency */
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counter_freq = plat_get_syscnt_freq();
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write_cntfrq_el0(counter_freq);
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}
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/*******************************************************************************
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* Detect what the security state of the next EL is and setup the minimum
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* required architectural state: program SCTRL to reflect the RES1 bits, and to
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* have MMU and caches disabled
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******************************************************************************/
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void bl31_next_el_arch_setup(uint32_t security_state)
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{
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unsigned long id_aa64pfr0 = read_id_aa64pfr0_el1();
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unsigned long next_sctlr;
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unsigned long el_status;
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unsigned long scr = read_scr();
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/* Use the same endianness than the current BL */
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next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
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/* Find out which EL we are going to */
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el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) & ID_AA64PFR0_ELX_MASK;
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if (security_state == NON_SECURE) {
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/* Check if EL2 is supported */
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if (el_status && (scr & SCR_HCE_BIT)) {
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/* Set SCTLR EL2 */
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next_sctlr |= SCTLR_EL2_RES1;
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write_sctlr_el2(next_sctlr);
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return;
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}
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}
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/*
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* SCTLR_EL1 needs the same programming irrespective of the
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* security state of EL1.
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*/
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next_sctlr |= SCTLR_EL1_RES1;
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write_sctlr_el1(next_sctlr);
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}
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