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https://github.com/ARM-software/arm-trusted-firmware.git
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9acaaded3c
BL2 requires the ability to access the TCG Event Log during Measured Boot. Currently the Platform hangs since the Event Log is not exposed to BL2's mmap. Define a RPI3_BL1_RW region to be added to the BL2 Image, if Measured Boot is enabled. Change-Id: Ic236a80e73ea342b4590cfb65bafbb8ffac17085 Signed-off-by: Abhi Singh <abhi.singh@arm.com>
283 lines
8.1 KiB
C
283 lines
8.1 KiB
C
/*
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* Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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#include "rpi_hw.h"
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
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#define PLATFORM_STACK_SIZE ULL(0x1000)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
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#define RPI_PRIMARY_CPU U(0)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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/* Local power state for power domains in Run state. */
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#define PLAT_LOCAL_STATE_RUN U(0)
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/* Local power state for retention. Valid only for CPU power domains */
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#define PLAT_LOCAL_STATE_RET U(1)
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/*
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* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains.
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*/
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#define PLAT_LOCAL_STATE_OFF U(2)
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define PLAT_LOCAL_PSTATE_WIDTH U(4)
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#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT U(6)
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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/*
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* Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and
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* secure DRAM. Note that this is all actually DRAM with different names,
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* there is no Secure RAM in the Raspberry Pi 3.
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*/
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#if RPI3_USE_UEFI_MAP
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#define SEC_ROM_BASE ULL(0x00000000)
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#define SEC_ROM_SIZE ULL(0x00010000)
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/* FIP placed after ROM to append it to BL1 with very little padding. */
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#define PLAT_RPI3_FIP_BASE ULL(0x00020000)
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#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000)
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/* Reserve 2M of secure SRAM and DRAM, starting at 2M */
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#define SEC_SRAM_BASE ULL(0x00200000)
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#define SEC_SRAM_SIZE ULL(0x00100000)
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#define SEC_DRAM0_BASE ULL(0x00300000)
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#define SEC_DRAM0_SIZE ULL(0x00100000)
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/* Windows on ARM requires some RAM at 4M */
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#define NS_DRAM0_BASE ULL(0x00400000)
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#define NS_DRAM0_SIZE ULL(0x00C00000)
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#else
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#define SEC_ROM_BASE ULL(0x00000000)
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#define SEC_ROM_SIZE ULL(0x00020000)
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/* FIP placed after ROM to append it to BL1 with very little padding. */
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#define PLAT_RPI3_FIP_BASE ULL(0x00020000)
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#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000)
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/* We have 16M of memory reserved starting at 256M */
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#define SEC_SRAM_BASE ULL(0x10000000)
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#define SEC_SRAM_SIZE ULL(0x00100000)
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#define SEC_DRAM0_BASE ULL(0x10100000)
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#define SEC_DRAM0_SIZE ULL(0x00F00000)
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/* End of reserved memory */
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#define NS_DRAM0_BASE ULL(0x11000000)
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#define NS_DRAM0_SIZE ULL(0x01000000)
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#endif /* RPI3_USE_UEFI_MAP */
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/*
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* BL33 entrypoint.
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*/
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#define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE
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#define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE
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/*
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* I/O registers.
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*/
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#define DEVICE0_BASE RPI_IO_BASE
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#define DEVICE0_SIZE RPI_IO_SIZE
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/*
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* Arm TF lives in SRAM, partition it here
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*/
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#define SHARED_RAM_BASE SEC_SRAM_BASE
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#define SHARED_RAM_SIZE ULL(0x00001000)
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#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
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#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
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/*
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* Mailbox to control the secondary cores.All secondary cores are held in a wait
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* loop in cold boot. To release them perform the following steps (plus any
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* additional barriers that may be needed):
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*
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* uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT;
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* *entrypoint = ADDRESS_TO_JUMP_TO;
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*
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* uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
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* mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO;
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*
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* sev();
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*/
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#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
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/* The secure entry point to be used on warm reset by all CPUs. */
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#define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE
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#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
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/* Hold entries for each CPU. */
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#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \
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PLAT_RPI3_TM_ENTRYPOINT_SIZE)
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#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
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#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \
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PLATFORM_CORE_COUNT)
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#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \
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PLAT_RPI3_TM_HOLD_SIZE)
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#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
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#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
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#define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)
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/*
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* BL1 specific defines.
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*
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
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* addresses.
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*
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* Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
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* the current BL1 RW debug size plus a little space for growth.
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*/
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#define PLAT_MAX_BL1_RW_SIZE ULL(0x12000)
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#define BL1_RO_BASE SEC_ROM_BASE
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#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
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#define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE)
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#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
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/*
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* In order to access the TCG Event Log in BL2, we need to expose the BL1_RW region
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* where the log resides.
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*/
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#define RPI3_MAP_BL1_RW MAP_REGION_FLAT(BL1_RW_BASE, \
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BL1_RW_LIMIT - BL1_RW_BASE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* BL2 specific defines.
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*
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* Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define PLAT_MAX_BL2_SIZE ULL(0x2C000)
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#define BL2_BASE (BL2_LIMIT - PLAT_MAX_BL2_SIZE)
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#define BL2_LIMIT BL31_BASE
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/*
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* BL31 specific defines.
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*
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* Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL31 debug size plus a little space for growth.
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*/
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#define PLAT_MAX_BL31_SIZE ULL(0x20000)
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#define BL31_BASE (BL31_LIMIT - PLAT_MAX_BL31_SIZE)
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#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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/*
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* BL32 specific defines.
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*
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* BL32 can execute from Secure SRAM or Secure DRAM.
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*/
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#define BL32_SRAM_BASE BL_RAM_BASE
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#define BL32_SRAM_LIMIT BL31_BASE
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#define BL32_DRAM_BASE SEC_DRAM0_BASE
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#define BL32_DRAM_LIMIT (SEC_DRAM0_BASE + SEC_DRAM0_SIZE)
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#ifdef SPD_opteed
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/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
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#define RPI3_OPTEE_PAGEABLE_LOAD_SIZE 0x080000 /* 512KB */
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#define RPI3_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - \
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RPI3_OPTEE_PAGEABLE_LOAD_SIZE)
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#endif
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#define SEC_SRAM_ID 0
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#define SEC_DRAM_ID 1
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#if RPI3_BL32_RAM_LOCATION_ID == SEC_SRAM_ID
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# define BL32_MEM_BASE BL_RAM_BASE
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# define BL32_MEM_SIZE BL_RAM_SIZE
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# define BL32_BASE BL32_SRAM_BASE
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# define BL32_LIMIT BL32_SRAM_LIMIT
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#elif RPI3_BL32_RAM_LOCATION_ID == SEC_DRAM_ID
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# define BL32_MEM_BASE SEC_DRAM0_BASE
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# define BL32_MEM_SIZE SEC_DRAM0_SIZE
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# define BL32_BASE BL32_DRAM_BASE
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# define BL32_LIMIT BL32_DRAM_LIMIT
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#else
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# error "Unsupported RPI3_BL32_RAM_LOCATION_ID value"
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#endif
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#define BL32_SIZE (BL32_LIMIT - BL32_BASE)
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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/*
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* Other memory-related defines.
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
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#define MAX_MMAP_REGIONS 8
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#define MAX_XLAT_TABLES 4
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_HANDLES U(4)
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#define MAX_IO_BLOCK_DEVICES U(1)
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/*
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* Serial-related constants.
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*/
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#define PLAT_RPI_MINI_UART_BASE RPI3_MINI_UART_BASE
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#define PLAT_RPI_PL011_UART_BASE RPI3_PL011_UART_BASE
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#define PLAT_RPI_PL011_UART_CLOCK RPI3_PL011_UART_CLOCK
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#define PLAT_RPI_UART_BAUDRATE ULL(115200)
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#define PLAT_RPI_CRASH_UART_BASE PLAT_RPI_MINI_UART_BASE
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/*
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* System counter
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*/
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#define SYS_COUNTER_FREQ_IN_TICKS ULL(19200000)
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/*
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* TCG Event Log
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*/
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#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400)
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/*
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* NT_FW_CONFIG magic dram addr and max size
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*/
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#define PLAT_RPI3_DTO_BASE ULL(0x11530000)
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#define PLAT_RPI3_DTO_MAX_SIZE ULL(0x001000)
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#endif /* PLATFORM_DEF_H */
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