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511148ef50
Cortex-X925 erratum 3701747 that applies to r0p0, r0p1 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/109180/latest/ Change-Id: I080296666f89276b3260686c2bdb8de63fc174c1 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
33 lines
1.2 KiB
C
33 lines
1.2 KiB
C
/*
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* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X925_H
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#define CORTEX_X925_H
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#define CORTEX_X925_MIDR U(0x410FD850)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X925_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_X925_CPUECTLR_EL1_EXTLLC_BIT U(0)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X925_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary control register 6 specific definitions
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******************************************************************************/
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#define CORTEX_X925_CPUACTLR6_EL1 S3_0_C15_C8_1
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#ifndef __ASSEMBLER__
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long check_erratum_cortex_x925_3701747(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_X925_H */
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