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77feb745e4
Cortex-X3 erratum 3701769 that applies to r0p0, r1p0, r1p1 and r1p2 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2055130/latest/ Change-Id: Ifd722e1bb8616ada2ad158297a7ca80b19a3370b Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
70 lines
3 KiB
C
70 lines
3 KiB
C
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X3_H
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#define CORTEX_X3_H
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#define CORTEX_X3_MIDR U(0x410FD4E0)
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/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X3_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4)
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#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR_EL1 S3_0_C15_C1_0
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
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#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
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/*******************************************************************************
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* CPU Auxiliary Control register 6 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR6_EL1 S3_0_C15_C8_1
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/*******************************************************************************
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* CPU Extended Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11)
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#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
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/*******************************************************************************
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* CPU Auxiliary Control register 3 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2
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#define CORTEX_X3_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
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#ifndef __ASSEMBLER__
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long check_erratum_cortex_x3_3701769(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_X3_H */
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