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26437afde1
Cortex-A715 erratum 3699560 that applies to all revisions <= r1p3 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2148827/latest/ Change-Id: I183aa921b4b6f715d64eb6b70809de2566017d31 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
45 lines
1.7 KiB
C
45 lines
1.7 KiB
C
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A715_H
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#define CORTEX_A715_H
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#define CORTEX_A715_MIDR U(0x410FD4D0)
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/* Cortex-A715 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A715_BHB_LOOP_COUNT U(38)
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/*******************************************************************************
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* CPU Auxiliary Control register 1 specific definitions.
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******************************************************************************/
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#define CORTEX_A715_CPUACTLR_EL1 S3_0_C15_C1_0
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A715_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_A715_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_A715_CPUPOR_EL3 S3_6_C15_C8_2
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#define CORTEX_A715_CPUPMR_EL3 S3_6_C15_C8_3
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#ifndef __ASSEMBLER__
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long check_erratum_cortex_a715_3699560(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_A715_H */
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