laurenw-arm 80942622fe Neoverse N1 Errata Workaround 1542419 ... Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6		2019-10-04 19:31:24 +03:00
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aarch64	Neoverse N1 Errata Workaround 1542419	2019-10-04 19:31:24 +03:00
bl31.ld.S	locks: linker variables to calculate per-cpu bakery lock size	2019-02-07 09:00:52 -08:00
bl31.mk	Add support for Branch Target Identification	2019-05-24 14:44:45 +01:00
bl31_context_mgmt.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
bl31_main.c	Refactor ARMv8.3 Pointer Authentication support code	2019-09-13 14:11:59 +01:00
ehf.c	Minor changes to documentation and comments	2019-02-28 13:35:21 +00:00
interrupt_mgmt.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00