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https://github.com/ARM-software/arm-trusted-firmware.git
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97043ac98e
Reduce the number of header files included from other header files as much as possible without splitting the files. Use forward declarations where possible. This allows removal of some unnecessary "#ifndef __ASSEMBLY__" statements. Also, review the .c and .S files for which header files really need including and reorder the #include statements alphabetically. Fixes ARM-software/tf-issues#31 Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
267 lines
8.1 KiB
ArmAsm
267 lines
8.1 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <tsp.h>
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.globl tsp_entrypoint
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.globl tsp_cpu_on_entry
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.globl tsp_cpu_off_entry
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.globl tsp_cpu_suspend_entry
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.globl tsp_cpu_resume_entry
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.globl tsp_fast_smc_entry
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/* ---------------------------------------------
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* Populate the params in x0-x7 from the pointer
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* to the smc args structure in x0.
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* ---------------------------------------------
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*/
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.macro restore_args_call_smc
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ldp x6, x7, [x0, #TSP_ARG6]
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ldp x4, x5, [x0, #TSP_ARG4]
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ldp x2, x3, [x0, #TSP_ARG2]
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ldp x0, x1, [x0, #TSP_ARG0]
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smc #0
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.endm
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func tsp_entrypoint
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/*---------------------------------------------
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* Store the extents of the tzram available to
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* BL32 for future use.
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* TODO: We are assuming that x9-x10 will not be
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* corrupted by any function before platform
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* setup.
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* ---------------------------------------------
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*/
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mov x9, x0
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mov x10, x1
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/* ---------------------------------------------
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* The entrypoint is expected to be executed
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* only by the primary cpu (at least for now).
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* So, make sure no secondary has lost its way.
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* ---------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_is_primary_cpu
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cbz x0, tsp_entrypoint_panic
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, early_exceptions
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msr vbar_el1, x0
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/* ---------------------------------------------
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* Enable the instruction cache.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el1
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orr x0, x0, #SCTLR_I_BIT
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msr sctlr_el1, x0
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isb
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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/* --------------------------------------------
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* Give ourselves a small coherent stack to
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* ease the pain of initializing the MMU
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* --------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_coherent_stack
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/* ---------------------------------------------
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* Perform early platform setup & platform
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* specific early arch. setup e.g. mmu setup
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* ---------------------------------------------
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*/
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mov x0, x9
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mov x1, x10
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bl bl32_early_platform_setup
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bl bl32_plat_arch_setup
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/* ---------------------------------------------
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* Give ourselves a stack allocated in Normal
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* -IS-WBWA memory
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* ---------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_stack
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl tsp_main
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/* ---------------------------------------------
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* Tell TSPD that we are done initialising
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* ---------------------------------------------
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*/
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mov x1, x0
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mov x0, #TSP_ENTRY_DONE
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smc #0
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tsp_entrypoint_panic:
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b tsp_entrypoint_panic
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu is to be turned off through a CPU_OFF
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* psci call to ask the TSP to perform any
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* bookeeping necessary. In the current
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* implementation, the TSPD expects the TSP to
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* re-initialise its state so nothing is done
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* here except for acknowledging the request.
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* ---------------------------------------------
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*/
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func tsp_cpu_off_entry
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bl tsp_cpu_off_main
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restore_args_call_smc
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu is turned on using a CPU_ON psci call to
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* ask the TSP to initialise itself i.e. setup
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* the mmu, stacks etc. Minimal architectural
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* state will be initialised by the TSPD when
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* this function is entered i.e. Caches and MMU
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* will be turned off, the execution state
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* will be aarch64 and exceptions masked.
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* ---------------------------------------------
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*/
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func tsp_cpu_on_entry
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, early_exceptions
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msr vbar_el1, x0
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/* ---------------------------------------------
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* Enable the instruction cache.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el1
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orr x0, x0, #SCTLR_I_BIT
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msr sctlr_el1, x0
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isb
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/* --------------------------------------------
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* Give ourselves a small coherent stack to
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* ease the pain of initializing the MMU
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* --------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_coherent_stack
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/* ---------------------------------------------
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* Initialise the MMU
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* ---------------------------------------------
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*/
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bl enable_mmu
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/* ---------------------------------------------
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* Give ourselves a stack allocated in Normal
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* -IS-WBWA memory
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* ---------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_stack
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/* ---------------------------------------------
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* Enter C runtime to perform any remaining
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* book keeping
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* ---------------------------------------------
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*/
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bl tsp_cpu_on_main
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restore_args_call_smc
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/* Should never reach here */
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tsp_cpu_on_entry_panic:
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b tsp_cpu_on_entry_panic
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu is to be suspended through a CPU_SUSPEND
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* psci call to ask the TSP to perform any
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* bookeeping necessary. In the current
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* implementation, the TSPD saves and restores
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* the EL1 state.
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* ---------------------------------------------
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*/
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func tsp_cpu_suspend_entry
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bl tsp_cpu_suspend_main
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restore_args_call_smc
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu resumes execution after an earlier
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* CPU_SUSPEND psci call to ask the TSP to
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* restore its saved context. In the current
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* implementation, the TSPD saves and restores
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* EL1 state so nothing is done here apart from
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* acknowledging the request.
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* ---------------------------------------------
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*/
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func tsp_cpu_resume_entry
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bl tsp_cpu_resume_main
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restore_args_call_smc
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tsp_cpu_resume_panic:
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b tsp_cpu_resume_panic
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/*---------------------------------------------
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* This entrypoint is used by the TSPD to ask
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* the TSP to service a fast smc request.
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* ---------------------------------------------
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*/
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func tsp_fast_smc_entry
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bl tsp_fast_smc_handler
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restore_args_call_smc
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tsp_fast_smc_entry_panic:
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b tsp_fast_smc_entry_panic
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