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95e4908e17
STM32MP_EMMC_BOOT allowed placing SSBL into the eMMC boot partition along with FSBL. This allows atomic update of both FSBL and SSBL at the same time. Previously, this was only possible for the FSBL, as the eMMC layout expected by TF-A had a single SSBL GPT partition in the eMMC user area. TEE binaries remained in dedicated GPT partitions whether STM32MP_EMMC_BOOT was on or off. The new FIP format collects SSBL and TEE partitions into a single binary placed into a GPT partition. Extend STM32MP_EMMC_BOOT, so eMMC-booted TF-A first uses a FIP image placed at offset 256K into the active eMMC boot partition. If no FIP magic is detected at that offset or if STM32MP_EMMC_BOOT is disabled, the GPT on the eMMC user area will be consulted as before. This allows power fail-safe update of all firmware using the built-in eMMC boot selector mechanism, provided it fits into the boot partition - SZ_256K. SZ_256K was chosen because it's the same offset used with the legacy format and because it's the size of the on-chip SRAM, where the STM32MP15x BootROM loads TF-A into. As such, TF-A may not exceed this size limit for existing SoCs. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Change-Id: Id7bec45652b3a289ca632d38d4b51316c5efdf8d
107 lines
3.2 KiB
C
107 lines
3.2 KiB
C
/*
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* Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_FIP_DEF_H
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#define STM32MP1_FIP_DEF_H
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#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
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#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
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#if STM32MP13
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#define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */
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#define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */
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#define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */
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#endif /* STM32MP13 */
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#if STM32MP15
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#define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */
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#define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */
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#define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */
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#endif /* STM32MP15 */
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#define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */
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#define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
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#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */
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#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */
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#if STM32MP13
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#define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \
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STM32MP_BL2_DTB_SIZE)
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#endif /* STM32MP13 */
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#if STM32MP15
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#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL2_SIZE)
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#endif /* STM32MP15 */
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#define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
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#define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
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STM32MP_BL2_RO_SIZE)
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#if STM32MP13
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#define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
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STM32MP_SYSRAM_SIZE - \
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STM32MP_BL2_RW_BASE)
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#define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE
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#endif /* STM32MP13 */
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#if STM32MP15
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#define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL2_RW_BASE)
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#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
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STM32MP_BL2_DTB_SIZE)
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#endif /* STM32MP15 */
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#define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE
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#define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \
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STM32MP_BL32_DTB_SIZE)
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#if defined(IMAGE_BL2)
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#define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
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#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
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#endif
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#if defined(IMAGE_BL32)
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#define STM32MP_DTB_SIZE STM32MP_BL32_DTB_SIZE
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#define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE
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#endif
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE
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#define STM32MP_OPTEE_SIZE (STM32MP_BL2_DTB_BASE - \
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STM32MP_OPTEE_BASE)
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#endif
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#if STM32MP13
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#define STM32MP_FW_CONFIG_BASE SRAM3_BASE
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#endif /* STM32MP13 */
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#if STM32MP15
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#define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \
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STM32MP_SYSRAM_SIZE - \
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PAGE_SIZE)
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#endif /* STM32MP15 */
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#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
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STM32MP_BL33_MAX_SIZE)
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/*
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* MAX_MMAP_REGIONS is usually:
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* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
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*/
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#if defined(IMAGE_BL32)
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#define MAX_MMAP_REGIONS 10
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#endif
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/*******************************************************************************
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* STM32MP1 RAW partition offset for devices without GPT
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******************************************************************************/
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#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
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#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
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#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
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#endif /* STM32MP1_FIP_DEF_H */
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