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https://github.com/ARM-software/arm-trusted-firmware.git
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93c78ed231
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <debug.h>
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#include <mce.h>
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#include <mmio.h>
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#include <string.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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#define MISCREG_CPU_RESET_VECTOR 0x2000
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#define MISCREG_AA64_RST_LOW 0x2004
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#define MISCREG_AA64_RST_HIGH 0x2008
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#define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658
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#define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65C
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#define CPU_RESET_MODE_AA64 1
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extern void memcpy16(void *dest, const void *src, unsigned int length);
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t __tegra186_cpu_reset_handler_end;
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/*******************************************************************************
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* Setup secondary CPU vectors
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******************************************************************************/
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void plat_secondary_setup(void)
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{
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uint32_t addr_low, addr_high;
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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uint64_t cpu_reset_handler_base;
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INFO("Setting up secondary CPU boot\n");
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if ((tegra_bl31_phys_base >= TEGRA_TZRAM_BASE) &&
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(tegra_bl31_phys_base <= (TEGRA_TZRAM_BASE + TEGRA_TZRAM_SIZE))) {
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/*
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* The BL31 code resides in the TZSRAM which loses state
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* when we enter System Suspend. Copy the wakeup trampoline
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* code to TZDRAM to help us exit from System Suspend.
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*/
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cpu_reset_handler_base = params_from_bl2->tzdram_base;
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memcpy16((void *)((uintptr_t)cpu_reset_handler_base),
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(void *)(uintptr_t)tegra186_cpu_reset_handler,
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(uintptr_t)&__tegra186_cpu_reset_handler_end -
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(uintptr_t)tegra186_cpu_reset_handler);
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} else {
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cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint;
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}
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addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64;
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addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff);
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/* write lower 32 bits first, then the upper 11 bits */
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
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/* save reset vector to be used during SYSTEM_SUSPEND exit */
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0,
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addr_low);
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1,
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addr_high);
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/* update reset vector address to the CCPLEX */
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mce_update_reset_vector();
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}
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