mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 18:14:24 +00:00
93c78ed231
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
478 lines
21 KiB
C
478 lines
21 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __MEMCTRLV2_H__
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#define __MEMCTRLV2_H__
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#include <tegra_def.h>
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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/*******************************************************************************
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* StreamID to indicate no SMMU translations (requests to be steered on the
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* SMMU bypass path)
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******************************************************************************/
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#define MC_STREAM_ID_MAX 0x7F
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/*******************************************************************************
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* Stream ID Override Config registers
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******************************************************************************/
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#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000
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#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070
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#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8
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#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0
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#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0
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#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8
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#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138
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#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158
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#define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188
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#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8
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#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8
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#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8
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#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220
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#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230
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#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268
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#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0
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#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8
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#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0
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#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338
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#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360
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#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368
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#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390
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#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0
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#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8
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#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0
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#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8
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#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0
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#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8
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#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400
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#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408
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#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420
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#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428
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#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430
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#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438
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#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440
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#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448
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#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460
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#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468
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#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470
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#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478
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#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480
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#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488
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#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490
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#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498
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#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0
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#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8
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#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0
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#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8
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#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0
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#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8
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#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0
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#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8
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#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0
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#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8
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#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0
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#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8
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#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500
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#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508
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#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510
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#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518
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/*******************************************************************************
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* Macro to calculate Security cfg register addr from StreamID Override register
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******************************************************************************/
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#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t))
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/*******************************************************************************
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* Memory Controller transaction override config registers
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******************************************************************************/
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#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8
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#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0
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#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000
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#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490
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#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478
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#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8
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#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328
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#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360
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#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8
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#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0
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#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460
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#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330
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#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470
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#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8
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#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318
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#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510
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#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8
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#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308
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#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468
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#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260
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#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480
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#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8
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#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8
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#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8
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#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258
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#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438
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#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440
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#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8
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#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448
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#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0
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#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500
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#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0
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#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0
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#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420
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#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408
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#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0
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#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0
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#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430
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#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0
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#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0
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#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518
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#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250
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#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230
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#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400
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#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8
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#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8
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#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320
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#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8
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#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8
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#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488
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#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8
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#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8
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#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428
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#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368
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#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158
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#define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300
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#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508
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#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238
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#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498
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#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310
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#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268
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#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0
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#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188
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#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0
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/*******************************************************************************
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* Structure to hold the transaction override settings to use to override
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* client inputs
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******************************************************************************/
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typedef struct mc_txn_override_cfg {
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uint32_t offset;
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uint8_t cgid_tag;
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} mc_txn_override_cfg_t;
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#define mc_make_txn_override_cfg(off, val) \
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{ \
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.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
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.cgid_tag = MC_TXN_OVERRIDE_ ## val \
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}
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/*******************************************************************************
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* Structure to hold the Stream ID to use to override client inputs
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******************************************************************************/
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typedef struct mc_streamid_override_cfg {
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uint32_t offset;
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uint8_t stream_id;
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} mc_streamid_override_cfg_t;
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/*******************************************************************************
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* Structure to hold the Stream ID Security Configuration settings
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******************************************************************************/
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typedef struct mc_streamid_security_cfg {
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char *name;
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uint32_t offset;
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int override_enable;
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int override_client_inputs;
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int override_client_ns_flag;
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} mc_streamid_security_cfg_t;
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#define OVERRIDE_DISABLE 1
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#define OVERRIDE_ENABLE 0
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#define CLIENT_FLAG_SECURE 0
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#define CLIENT_FLAG_NON_SECURE 1
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#define CLIENT_INPUTS_OVERRIDE 1
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#define CLIENT_INPUTS_NO_OVERRIDE 0
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#define mc_make_sec_cfg(off, ns, ovrrd, access) \
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{ \
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.name = # off, \
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.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
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MC_STREAMID_OVERRIDE_CFG_ ## off), \
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.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
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.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
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.override_enable = OVERRIDE_ ## access \
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}
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/*******************************************************************************
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* Structure to hold Memory Controller's Configuration settings
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******************************************************************************/
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typedef struct tegra_mc_settings {
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const uint32_t *streamid_override_cfg;
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uint32_t num_streamid_override_cfgs;
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const mc_streamid_security_cfg_t *streamid_security_cfg;
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uint32_t num_streamid_security_cfgs;
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const mc_txn_override_cfg_t *txn_override_cfg;
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uint32_t num_txn_override_cfgs;
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} tegra_mc_settings_t;
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#endif /* __ASSEMBLY__ */
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/*******************************************************************************
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* Memory Controller SMMU Bypass config register
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******************************************************************************/
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#define MC_SMMU_BYPASS_CONFIG 0x1820
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#define MC_SMMU_BYPASS_CTRL_MASK 0x3
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#define MC_SMMU_BYPASS_CTRL_SHIFT 0
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#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31)
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#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
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MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
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#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1 << 0)
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#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2 << 4)
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#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1 << 12)
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/*******************************************************************************
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* Non-SO_DEV transactions override values for CGID_TAG bitfield for the
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* MC_TXN_OVERRIDE_CONFIG_{module} registers
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******************************************************************************/
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#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0
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#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1
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#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2
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#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3
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#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3
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/*******************************************************************************
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* Memory Controller Reset Control registers
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******************************************************************************/
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#define MC_CLIENT_HOTRESET_CTRL0 0x200
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#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0
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#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1 << 0)
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#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1 << 6)
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#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1 << 7)
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#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1 << 8)
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#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1 << 9)
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#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1 << 11)
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#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1 << 15)
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#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1 << 17)
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#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1 << 18)
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#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1 << 19)
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#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1 << 20)
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#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1 << 22)
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#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1 << 29)
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#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1 << 30)
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#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1 << 31)
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#define MC_CLIENT_HOTRESET_STATUS0 0x204
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#define MC_CLIENT_HOTRESET_CTRL1 0x970
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#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0
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#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1 << 0)
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#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1 << 2)
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#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1 << 5)
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#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1 << 6)
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#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1 << 7)
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#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1 << 8)
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#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1 << 12)
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#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1 << 13)
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#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1 << 18)
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#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1 << 19)
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#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1 << 20)
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#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1 << 21)
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#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1 << 22)
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#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1 << 23)
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#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1 << 24)
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#define MC_CLIENT_HOTRESET_STATUS1 0x974
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/*******************************************************************************
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* Memory Controller's PCFIFO client configuration registers
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******************************************************************************/
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#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
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#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0 << 17)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1 << 17)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0 << 21)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1 << 21)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0 << 29)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1 << 29)
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#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
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#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000
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#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0 << 11)
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#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1 << 11)
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#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0 << 13)
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#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1 << 13)
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#define MC_PCFIFO_CLIENT_CONFIG3 0xddc
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#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0
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#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0 << 7)
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#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1 << 7)
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#define MC_PCFIFO_CLIENT_CONFIG4 0xde0
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#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0 << 1)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1 << 1)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0 << 5)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1 << 5)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0 << 13)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1 << 13)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0 << 15)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1 << 15)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0 << 17)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1 << 17)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0 << 22)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1 << 22)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0 << 26)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1 << 26)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0 << 30)
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#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1 << 30)
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#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4
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#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0
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#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0 << 0)
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#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1 << 0)
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/*******************************************************************************
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* Memory Controller's SMMU client configuration registers
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******************************************************************************/
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#define MC_SMMU_CLIENT_CONFIG1 0x44
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#define MC_SMMU_CLIENT_CONFIG1_RESET_VAL 0x20000
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#define MC_SMMU_CLIENT_CONFIG1_AFIW_UNORDERED (0 << 17)
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#define MC_SMMU_CLIENT_CONFIG1_AFIW_MASK (1 << 17)
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#define MC_SMMU_CLIENT_CONFIG1_HDAW_UNORDERED (0 << 21)
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#define MC_SMMU_CLIENT_CONFIG1_HDAW_MASK (1 << 21)
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#define MC_SMMU_CLIENT_CONFIG1_SATAW_UNORDERED (0 << 29)
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#define MC_SMMU_CLIENT_CONFIG1_SATAW_MASK (1 << 29)
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#define MC_SMMU_CLIENT_CONFIG2 0x48
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#define MC_SMMU_CLIENT_CONFIG2_RESET_VAL 0x20000
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#define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_UNORDERED (0 << 11)
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#define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_MASK (1 << 11)
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#define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_UNORDERED (0 << 13)
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#define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_MASK (1 << 13)
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#define MC_SMMU_CLIENT_CONFIG3 0x4c
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#define MC_SMMU_CLIENT_CONFIG3_RESET_VAL 0
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#define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_UNORDERED (0 << 7)
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#define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_MASK (1 << 7)
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#define MC_SMMU_CLIENT_CONFIG4 0xb9c
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#define MC_SMMU_CLIENT_CONFIG4_RESET_VAL 0
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#define MC_SMMU_CLIENT_CONFIG4_SESWR_UNORDERED (0 << 1)
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#define MC_SMMU_CLIENT_CONFIG4_SESWR_MASK (1 << 1)
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#define MC_SMMU_CLIENT_CONFIG4_ETRW_UNORDERED (0 << 5)
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#define MC_SMMU_CLIENT_CONFIG4_ETRW_MASK (1 << 5)
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#define MC_SMMU_CLIENT_CONFIG4_AXISW_UNORDERED (0 << 13)
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#define MC_SMMU_CLIENT_CONFIG4_AXISW_MASK (1 << 13)
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#define MC_SMMU_CLIENT_CONFIG4_EQOSW_UNORDERED (0 << 15)
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#define MC_SMMU_CLIENT_CONFIG4_EQOSW_MASK (1 << 15)
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#define MC_SMMU_CLIENT_CONFIG4_UFSHCW_UNORDERED (0 << 17)
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#define MC_SMMU_CLIENT_CONFIG4_UFSHCW_MASK (1 << 17)
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#define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_UNORDERED (0 << 22)
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#define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_MASK (1 << 22)
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#define MC_SMMU_CLIENT_CONFIG4_AONDMAW_UNORDERED (0 << 26)
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#define MC_SMMU_CLIENT_CONFIG4_AONDMAW_MASK (1 << 26)
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#define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_UNORDERED (0 << 30)
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#define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_MASK (1 << 30)
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#define MC_SMMU_CLIENT_CONFIG5 0xbac
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#define MC_SMMU_CLIENT_CONFIG5_RESET_VAL 0
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#define MC_SMMU_CLIENT_CONFIG5_APEDMAW_UNORDERED (0 << 0)
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#define MC_SMMU_CLIENT_CONFIG5_APEDMAW_MASK (1 << 0)
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#ifndef __ASSEMBLY__
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#include <mmio.h>
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static inline uint32_t tegra_mc_read_32(uint32_t off)
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{
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return mmio_read_32(TEGRA_MC_BASE + off);
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}
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static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
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{
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mmio_write_32(TEGRA_MC_BASE + off, val);
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}
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static inline uint32_t tegra_mc_streamid_read_32(uint32_t off)
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{
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return mmio_read_32(TEGRA_MC_STREAMID_BASE + off);
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}
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|
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static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
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|
{
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mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
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}
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#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
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(~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
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MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
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#define mc_set_smmu_unordered_boot_so_mss(id, client) \
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(~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
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MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
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|
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#define mc_set_tsa_passthrough(client) \
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|
{ \
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mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
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(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
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~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
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TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
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|
}
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|
|
|
#define mc_set_forced_coherent_cfg(client) \
|
|
{ \
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|
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
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|
MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV); \
|
|
}
|
|
|
|
#define mc_set_forced_coherent_so_dev_cfg(client) \
|
|
{ \
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|
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
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|
MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \
|
|
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \
|
|
}
|
|
|
|
#define mc_set_forced_coherent_axid_so_dev_cfg(client) \
|
|
{ \
|
|
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
|
|
MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \
|
|
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \
|
|
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Handler to read memory configuration settings
|
|
*
|
|
* Implemented by SoCs under tegra/soc/txxx
|
|
******************************************************************************/
|
|
tegra_mc_settings_t *tegra_get_mc_settings(void);
|
|
|
|
#endif /* __ASSMEBLY__ */
|
|
|
|
#endif /* __MEMCTRLV2_H__ */
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