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93bb7a0ac3
The SCP firmware on the ARM FPGA initialises the UART already. This allows us to treat the PL011 as an SBSA Generic UART, which does not require any further setup. This in particular removes the need for any baudrate and base clock related settings to be hard coded into the BL31 image. Change-Id: I16fc943526267356b97166a7068459e06ff77f0f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
36 lines
1.1 KiB
C
36 lines
1.1 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/utils_def.h>
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#ifndef FPGA_DEF_H
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#define FPGA_DEF_H
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/*
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* These are set to large values to account for images describing systems with
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* larger cluster configurations.
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*
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* For cases where the number of clusters, cores or threads is smaller than a
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* maximum value below, this does not affect the PSCI functionality as any PEs
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* that are present will still be indexed appropriately regardless of any empty
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* entries in the array used to represent the topology.
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*/
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#define FPGA_MAX_CLUSTER_COUNT 2
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#define FPGA_MAX_CPUS_PER_CLUSTER 8
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#define FPGA_MAX_PE_PER_CPU 4
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#define FPGA_PRIMARY_CPU 0x0
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/*******************************************************************************
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* FPGA image memory map related constants
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******************************************************************************/
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/* UART base address, as configured by the image */
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#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000
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#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
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#define FPGA_TIMER_FREQUENCY 10000000
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#endif
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