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https://github.com/ARM-software/arm-trusted-firmware.git
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b2bca61da5
This patch adds translation library supports for AArch32 platforms. The library only supports long descriptor formats for AArch32. The `enable_mmu_secure()` enables the MMU for secure world with `TTBR0` pointing to the populated translation tables. Change-Id: I061345b1779391d098e35e7fe0c76e3ebf850e08
201 lines
6.4 KiB
C
201 lines
6.4 KiB
C
/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __XLAT_TABLES_H__
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#define __XLAT_TABLES_H__
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/* Miscellaneous MMU related constants */
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#define NUM_2MB_IN_GB (1 << 9)
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#define NUM_4K_IN_2MB (1 << 9)
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#define NUM_GB_IN_4GB (1 << 2)
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#define TWO_MB_SHIFT 21
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#define ONE_GB_SHIFT 30
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#define FOUR_KB_SHIFT 12
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#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
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#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
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#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
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#define INVALID_DESC 0x0
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#define BLOCK_DESC 0x1
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#define TABLE_DESC 0x3
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#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
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#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
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#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
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#define LEVEL1 1
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#define LEVEL2 2
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#define LEVEL3 3
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#define XN (1ull << 2)
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#define PXN (1ull << 1)
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#define CONT_HINT (1ull << 0)
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#define UPPER_ATTRS(x) (x & 0x7) << 52
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#define NON_GLOBAL (1 << 9)
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#define ACCESS_FLAG (1 << 8)
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#define NSH (0x0 << 6)
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#define OSH (0x2 << 6)
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#define ISH (0x3 << 6)
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#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
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#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT)
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#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
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#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
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#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */
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#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT
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#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT)
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/* Values for number of entries in each MMU translation table */
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#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT)
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#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
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/* Values to convert a memory address to an index into a translation table */
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#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
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#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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/*
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* AP[1] bit is ignored by hardware and is
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* treated as if it is One in EL2/EL3
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*/
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#define AP_RO (0x1 << 5)
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#define AP_RW (0x0 << 5)
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#define NS (0x1 << 3)
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#define ATTR_NON_CACHEABLE_INDEX 0x2
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#define ATTR_DEVICE_INDEX 0x1
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#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
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#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
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#define ATTR_NON_CACHEABLE (0x44)
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#define ATTR_DEVICE (0x4)
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#define ATTR_IWBWA_OWBWA_NTR (0xff)
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#define MAIR_ATTR_SET(attr, index) (attr << (index << 3))
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/*
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* Flags to override default values used to program system registers while
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* enabling the MMU.
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*/
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#define DISABLE_DCACHE (1 << 0)
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#ifndef __ASSEMBLY__
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#include <stddef.h>
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#include <stdint.h>
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/* Helper macro to define entries for mmap_region_t. It creates
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* identity mappings for each region.
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*/
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#define MAP_REGION_FLAT(adr, sz, attr) MAP_REGION(adr, adr, sz, attr)
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/* Helper macro to define entries for mmap_region_t. It allows to
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* re-map address mappings from 'pa' to 'va' for each region.
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*/
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#define MAP_REGION(pa, va, sz, attr) {(pa), (va), (sz), (attr)}
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/*
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* Shifts and masks to access fields of an mmap_attr_t
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*/
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#define MT_TYPE_MASK 0x7
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#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK)
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/* Access permissions (RO/RW) */
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#define MT_PERM_SHIFT 3
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/* Security state (SECURE/NS) */
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#define MT_SEC_SHIFT 4
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/* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */
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#define MT_EXECUTE_SHIFT 5
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/*
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* Memory mapping attributes
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*/
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typedef enum {
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/*
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* Memory types supported.
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* These are organised so that, going down the list, the memory types
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* are getting weaker; conversely going up the list the memory types are
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* getting stronger.
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*/
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MT_DEVICE,
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MT_NON_CACHEABLE,
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MT_MEMORY,
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/* Values up to 7 are reserved to add new memory types in the future */
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MT_RO = 0 << MT_PERM_SHIFT,
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MT_RW = 1 << MT_PERM_SHIFT,
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MT_SECURE = 0 << MT_SEC_SHIFT,
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MT_NS = 1 << MT_SEC_SHIFT,
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/*
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* Access permissions for instruction execution are only relevant for
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* normal read-only memory, i.e. MT_MEMORY | MT_RO. They are ignored
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* (and potentially overridden) otherwise:
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* - Device memory is always marked as execute-never.
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* - Read-write normal memory is always marked as execute-never.
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*/
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MT_EXECUTE = 0 << MT_EXECUTE_SHIFT,
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MT_EXECUTE_NEVER = 1 << MT_EXECUTE_SHIFT,
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} mmap_attr_t;
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#define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE)
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#define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER)
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/*
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* Structure for specifying a single region of memory.
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*/
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typedef struct mmap_region {
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unsigned long long base_pa;
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uintptr_t base_va;
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size_t size;
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mmap_attr_t attr;
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} mmap_region_t;
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/* Generic translation table APIs */
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void init_xlat_tables(void);
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void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
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size_t size, unsigned int attr);
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void mmap_add(const mmap_region_t *mm);
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#ifdef AARCH32
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/* AArch32 specific translation table API */
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void enable_mmu_secure(uint32_t flags);
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#else
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/* AArch64 specific translation table APIs */
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void enable_mmu_el1(unsigned int flags);
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void enable_mmu_el3(unsigned int flags);
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#endif /* AARCH32 */
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#endif /*__ASSEMBLY__*/
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#endif /* __XLAT_TABLES_H__ */
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