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26a3351eda
Due to their interrelationship in the architecture the SVE and SME features in TF-A are mutually exclusive. This means that a single binary can't be shared between systems with and without SME if the system without SME does support SVE, SVE will not be initialised so lower ELs will run into trouble trying to use it. This unusual behaviour for TF-A which normally gracefully handles situations where features are enabled but not supported on the current hardware. Address this by calling the SVE enable and disable functions if SME is not supported rather than immediately exiting, these perform their own feature checks so if neither SVE nor SME is supported behaviour is unchanged. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I2c606202fa6c040069f44e29d36b5abb48391874
107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
/*
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* Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/extensions/sme.h>
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#include <lib/extensions/sve.h>
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static bool feat_sme_supported(void)
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{
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uint64_t features;
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features = read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SME_SHIFT;
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return (features & ID_AA64PFR1_EL1_SME_MASK) != 0U;
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}
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static bool feat_sme_fa64_supported(void)
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{
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uint64_t features;
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features = read_id_aa64smfr0_el1();
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return (features & ID_AA64SMFR0_EL1_FA64_BIT) != 0U;
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}
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void sme_enable(cpu_context_t *context)
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{
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u_register_t reg;
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u_register_t cptr_el3;
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el3_state_t *state;
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/* Make sure SME is implemented in hardware before continuing. */
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if (!feat_sme_supported()) {
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/* Perhaps the hardware supports SVE only */
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sve_enable(context);
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return;
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}
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/* Get the context state. */
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state = get_el3state_ctx(context);
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/* Enable SME in CPTR_EL3. */
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reg = read_ctx_reg(state, CTX_CPTR_EL3);
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reg |= ESM_BIT;
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write_ctx_reg(state, CTX_CPTR_EL3, reg);
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/* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */
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reg = read_ctx_reg(state, CTX_SCR_EL3);
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reg |= SCR_ENTP2_BIT;
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write_ctx_reg(state, CTX_SCR_EL3, reg);
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/* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */
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cptr_el3 = read_cptr_el3();
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write_cptr_el3(cptr_el3 | ESM_BIT);
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/*
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* Set the max LEN value and FA64 bit. This register is set up globally
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* to be the least restrictive, then lower ELs can restrict as needed
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* using SMCR_EL2 and SMCR_EL1.
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*/
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reg = SMCR_ELX_LEN_MASK;
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if (feat_sme_fa64_supported()) {
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VERBOSE("[SME] FA64 enabled\n");
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reg |= SMCR_ELX_FA64_BIT;
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}
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write_smcr_el3(reg);
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/* Reset CPTR_EL3 value. */
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write_cptr_el3(cptr_el3);
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/* Enable SVE/FPU in addition to SME. */
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sve_enable(context);
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}
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void sme_disable(cpu_context_t *context)
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{
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u_register_t reg;
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el3_state_t *state;
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/* Make sure SME is implemented in hardware before continuing. */
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if (!feat_sme_supported()) {
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/* Perhaps the hardware supports SVE only */
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sve_disable(context);
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return;
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}
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/* Get the context state. */
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state = get_el3state_ctx(context);
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/* Disable SME, SVE, and FPU since they all share registers. */
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reg = read_ctx_reg(state, CTX_CPTR_EL3);
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reg &= ~ESM_BIT; /* Trap SME */
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reg &= ~CPTR_EZ_BIT; /* Trap SVE */
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reg |= TFP_BIT; /* Trap FPU/SIMD */
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write_ctx_reg(state, CTX_CPTR_EL3, reg);
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/* Disable access to TPIDR2_EL0. */
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reg = read_ctx_reg(state, CTX_SCR_EL3);
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reg &= ~SCR_ENTP2_BIT;
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write_ctx_reg(state, CTX_SCR_EL3, reg);
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}
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