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https://github.com/ARM-software/arm-trusted-firmware.git
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fb9212be17
The number of gpc imr mask reg & the offset is different on some SOC, so correct it & replace the magic number with macro define. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74
129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GPC_REG_H
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#define GPC_REG_H
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#define LPCR_A53_BSC 0x0
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#define LPCR_A53_BSC2 0x108
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#define LPCR_A53_AD 0x4
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#define LPCR_M4 0x8
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#define SLPCR 0x14
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#define MST_CPU_MAPPING 0x18
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#define MLPCR 0x20
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#define PGC_ACK_SEL_A53 0x24
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#define IMR1_CORE0_A53 0x30
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#define IMR1_CORE1_A53 0x40
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#define IMR1_CORE2_A53 0x1C0
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#define IMR1_CORE3_A53 0x1D0
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#define IMR1_CORE0_M4 0x50
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#define SLT0_CFG 0xB0
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#define GPC_PU_PWRHSK 0x1FC
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#define PGC_CPU_0_1_MAPPING 0xEC
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#define CPU_PGC_UP_TRG 0xF0
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#define PU_PGC_UP_TRG 0xF8
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#define CPU_PGC_DN_TRG 0xFC
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#define PU_PGC_DN_TRG 0x104
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#define LPS_CPU1 0x114
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#define A53_CORE0_PGC 0x800
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#define A53_PLAT_PGC 0x900
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#define PLAT_PGC_PCR 0x900
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#define NOC_PGC_PCR 0xa40
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#define PGC_SCU_TIMING 0x910
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#define MASK_DSM_TRIGGER_A53 BIT(31)
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#define IRQ_SRC_A53_WUP BIT(30)
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#define IRQ_SRC_A53_WUP_SHIFT 30
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#define IRQ_SRC_C1 BIT(29)
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#define IRQ_SRC_C0 BIT(28)
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#define IRQ_SRC_C3 BIT(23)
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#define IRQ_SRC_C2 BIT(22)
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#define CPU_CLOCK_ON_LPM BIT(14)
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#define A53_CLK_ON_LPM BIT(14)
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#define MASTER0_LPM_HSK BIT(6)
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#define MASTER1_LPM_HSK BIT(7)
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#define MASTER2_LPM_HSK BIT(8)
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#define L2PGE BIT(31)
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#define EN_L2_WFI_PDN BIT(5)
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#define EN_PLAT_PDN BIT(4)
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#define SLPCR_EN_DSM BIT(31)
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#define SLPCR_RBC_EN BIT(30)
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#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17)
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#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16)
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#define SLPCR_VSTBY BIT(2)
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#define SLPCR_SBYOS BIT(1)
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#define SLPCR_BYPASS_PMIC_READY BIT(0)
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#define SLPCR_RBC_COUNT_SHIFT 24
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#define SLPCR_STBY_COUNT_SHFT 3
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#define A53_DUMMY_PDN_ACK BIT(15)
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#define A53_DUMMY_PUP_ACK BIT(31)
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#define A53_PLAT_PDN_ACK BIT(2)
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#define A53_PLAT_PUP_ACK BIT(18)
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#define NOC_PDN_SLT_CTRL BIT(10)
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#define NOC_PUP_SLT_CTRL BIT(11)
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#define NOC_PGC_PDN_ACK BIT(3)
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#define NOC_PGC_PUP_ACK BIT(19)
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#define PLAT_PUP_SLT_CTRL BIT(9)
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#define PLAT_PDN_SLT_CTRL BIT(8)
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#define SLT_PLAT_PDN BIT(8)
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#define SLT_PLAT_PUP BIT(9)
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#define MASTER1_MAPPING BIT(1)
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#define MASTER2_MAPPING BIT(2)
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#define MIPI_PWR_REQ BIT(0)
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#define PCIE_PWR_REQ BIT(1)
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#define OTG1_PWR_REQ BIT(2)
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#define OTG2_PWR_REQ BIT(3)
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#define HSIOMIX_PWR_REQ BIT(4)
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#define DDRMIX_PWR_REQ BIT(5)
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#define GPU2D_PWR_REQ BIT(6)
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#define GPUMIX_PWR_REQ BIT(7)
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#define VPUMIX_PWR_REQ BIT(8)
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#define GPU3D_PWR_REQ BIT(9)
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#define DISPMIX_PWR_REQ BIT(10)
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#define VPU_G1_PWR_REQ BIT(11)
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#define VPU_G2_PWR_REQ BIT(12)
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#define VPU_H1_PWR_REQ BIT(13)
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#define DDRMIX_ADB400_SYNC BIT(2)
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#define HSIOMIX_ADB400_SYNC (0x3 << 5)
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#define DISPMIX_ADB400_SYNC BIT(7)
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#define VPUMIX_ADB400_SYNC BIT(8)
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#define GPU3D_ADB400_SYNC BIT(9)
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#define GPU2D_ADB400_SYNC BIT(10)
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#define GPUMIX_ADB400_SYNC BIT(11)
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#define DDRMIX_ADB400_ACK BIT(20)
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#define HSIOMIX_ADB400_ACK (0x3 << 23)
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#define DISPMIX_ADB400_ACK BIT(25)
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#define VPUMIX_ADB400_ACK BIT(26)
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#define GPU3D_ADB400_ACK BIT(27)
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#define GPU2D_ADB400_ACK BIT(28)
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#define GPUMIX_ADB400_ACK BIT(29)
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#define MIPI_PGC 0xc00
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#define PCIE_PGC 0xc40
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#define OTG1_PGC 0xc80
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#define OTG2_PGC 0xcc0
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#define HSIOMIX_PGC 0xd00
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#define DDRMIX_PGC 0xd40
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#define GPU2D_PGC 0xd80
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#define GPUMIX_PGC 0xdc0
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#define VPUMIX_PGC 0xe00
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#define GPU3D_PGC 0xe40
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#define DISPMIX_PGC 0xe80
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#define VPU_G1_PGC 0xec0
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#define VPU_G2_PGC 0xf00
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#define VPU_H1_PGC 0xf40
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#define IRQ_IMR_NUM U(4)
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#endif /* GPC_REG_H */
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