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https://github.com/ARM-software/arm-trusted-firmware.git
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87639aab0b
Add 'firmware' node in morello-soc.dts to expose SCMI support to the kernel. The SCMI protocols supported at the moment are SCMI Base, Clock and Perf (DVFS). The current mailbox memory region in MHU SRAM has an issue with any access not aligned to a 4-byte boundary. So, the SCMI mailbox memory region has been relocated to AP non-trusted RAM to get around the problem. Signed-off-by: Anurag Koul <anurag.koul@arm.com> Change-Id: Ibcbce8823b751a0fc3be7e9bc3588c1dc47ae024
271 lines
6.4 KiB
Text
271 lines
6.4 KiB
Text
/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include "morello.dtsi"
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/ {
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chosen {
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stdout-path = "soc_uart0:115200n8";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure-firmware@ff000000 {
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reg = <0 0xff000000 0 0x01000000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu1@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu2@10000 {
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compatible = "arm,armv8";
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reg = <0x0 0x10000>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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};
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cpu3@10100 {
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compatible = "arm,armv8";
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reg = <0x0 0x10100>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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};
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};
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/* The first bank of memory, memory map is actually provided by UEFI. */
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memory@80000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x80000000-0xffffffff] */
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reg = <0x00000000 0x80000000 0x0 0x7F000000>;
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};
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memory@8080000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x8080000000-0x83f7ffffff] */
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reg = <0x00000080 0x80000000 0x3 0x78000000>;
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};
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smmu_pcie: iommu@4f400000 {
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compatible = "arm,smmu-v3";
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reg = <0 0x4f400000 0 0x40000>;
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interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
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msi-parent = <&its2 0>;
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#iommu-cells = <1>;
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dma-coherent;
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};
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pcie_ctlr: pcie@28c0000000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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reg = <0x28 0xC0000000 0 0x10000000>;
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bus-range = <0 255>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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dma-coherent;
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ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>,
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<0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>,
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<0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
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msi-map = <0 &its_pcie 0 0x10000>;
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iommu-map = <0 &smmu_pcie 0 0x10000>;
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status = "okay";
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};
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smmu_ccix: iommu@4f000000 {
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compatible = "arm,smmu-v3";
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reg = <0 0x4f000000 0 0x40000>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
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msi-parent = <&its1 0>;
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#iommu-cells = <1>;
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dma-coherent;
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};
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ccix_pcie_ctlr: pcie@4fc0000000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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reg = <0x4F 0xC0000000 0 0x10000000>;
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bus-range = <0 255>;
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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dma-coherent;
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ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>,
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<0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>,
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<0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
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msi-map = <0 &its_ccix 0 0x10000>;
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iommu-map = <0 &smmu_ccix 0 0x10000>;
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status = "okay";
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};
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smmu_dp: iommu@2ce00000 {
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compatible = "arm,smmu-v3";
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reg = <0 0x2ce00000 0 0x40000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "cmdq-sync", "gerror";
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#iommu-cells = <1>;
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};
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dp0: display@2cc00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "arm,mali-d32";
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reg = <0 0x2cc00000 0 0x20000>;
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interrupts = <0 69 4>;
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interrupt-names = "DPU";
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clocks = <&dpu_aclk>;
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clock-names = "aclk";
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iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
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<&smmu_dp 8>;
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pl0: pipeline@0 {
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reg = <0>;
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clocks = <&scmi_clk 1>;
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clock-names = "pxclk";
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pl_id = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dp_pl0_out0: endpoint {
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remote-endpoint = <&tda998x_0_input>;
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};
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};
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};
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};
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};
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i2c@1c0f0000 {
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compatible = "cdns,i2c-r1p14";
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reg = <0x0 0x1c0f0000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <500>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dpu_aclk>;
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hdmi-transmitter@70 {
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compatible = "nxp,tda998x";
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reg = <0x70>;
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video-ports = <0x234501>;
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port {
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tda998x_0_input: endpoint {
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remote-endpoint = <&dp_pl0_out0>;
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};
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};
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};
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};
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dpu_aclk: dpu_aclk {
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/* 77.1 MHz derived from 24 MHz reference clock */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <350000000>;
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clock-output-names = "aclk";
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};
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firmware {
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mailbox 1 0 &mailbox 1 1>;
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shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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};
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&gic {
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x300c0000 0 0x80000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its1: its@30040000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x30040000 0x0 0x20000>;
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};
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its2: its@30060000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x30060000 0x0 0x20000>;
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};
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its_ccix: its@30080000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x30080000 0x0 0x20000>;
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};
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its_pcie: its@300a0000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x300a0000 0x0 0x20000>;
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};
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};
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