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Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
31 lines
694 B
ArmAsm
31 lines
694 B
ArmAsm
/*
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* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <context.h>
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#if WORKAROUND_CVE_2022_23960
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/*
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* This macro applies the mitigation for CVE-2022-23960.
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* The macro saves x2-x3 to the CPU context.
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* SP should point to the CPU context.
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*/
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.macro apply_cve_2022_23960_bhb_wa _bhb_loop_count
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stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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/* CVE-BHB-NUM loop count */
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mov x2, \_bhb_loop_count
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1:
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/* b pc+4 part of the workaround */
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b 2f
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2:
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subs x2, x2, #1
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bne 1b
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dsb sy
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isb
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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.endm
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#endif /* WORKAROUND_CVE_2022_23960 */
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