mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-18 02:24:18 +00:00
1fe4a9d181
Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
421 lines
10 KiB
ArmAsm
421 lines
10 KiB
ArmAsm
/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* --------------------------------------------------
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* Errata Workaround for A78 Erratum 1688305.
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* This applies to revision r0p0 and r1p0 of A78.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1688305_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1688305
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cbz x0, 1f
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mrs x1, CORTEX_A78_ACTLR2_EL1
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orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
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msr CORTEX_A78_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a78_1688305_wa
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func check_errata_1688305
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1688305
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78 Errata #1941498.
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* This applies to revisions r0p0, r1p0, and r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1941498_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1941498
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cbz x0, 1f
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/* Set bit 8 in ECTLR_EL1 */
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mrs x1, CORTEX_A78_CPUECTLR_EL1
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orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
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msr CORTEX_A78_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a78_1941498_wa
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func check_errata_1941498
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/* Check for revision <= r1p1, might need to be updated later. */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1941498
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/* --------------------------------------------------
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* Errata Workaround for A78 Erratum 1951500.
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* This applies to revisions r1p0 and r1p1 of A78.
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* The issue also exists in r0p0 but there is no fix
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* in that revision.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1951500_wa
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/* Compare x0 against revisions r1p0 - r1p1 */
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mov x17, x30
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bl check_errata_1951500
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cbz x0, 1f
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msr S3_6_c15_c8_0, xzr
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ldr x0, =0x10E3900002
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #1
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #2
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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isb
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1:
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ret x17
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endfunc errata_a78_1951500_wa
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func check_errata_1951500
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/* Applies to revisions r1p0 and r1p1. */
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mov x1, #CPU_REV(1, 0)
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mov x2, #CPU_REV(1, 1)
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b cpu_rev_var_range
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endfunc check_errata_1951500
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78 Errata #1821534.
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* This applies to revisions r0p0 and r1p0.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1821534_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_1821534
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cbz x0, 1f
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/* Set bit 2 in ACTLR2_EL1 */
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mrs x1, CORTEX_A78_ACTLR2_EL1
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orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
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msr CORTEX_A78_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a78_1821534_wa
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func check_errata_1821534
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1821534
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78 Errata 1952683.
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* This applies to revision r0p0.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1952683_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_1952683
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cbz x0, 1f
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ldr x0,=0x5
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xEEE10A10
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0FFF
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x0010F000
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msr S3_6_c15_c8_4,x0
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ldr x0,=0x0010F000
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msr S3_6_c15_c8_5,x0
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ldr x0,=0x40000080023ff
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msr S3_6_c15_c8_1,x0
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ldr x0,=0x6
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xEE640F34
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0FFF
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x40000080023ff
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msr S3_6_c15_c8_1,x0
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isb
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1:
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ret x17
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endfunc errata_a78_1952683_wa
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func check_errata_1952683
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/* Applies to r0p0 only */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_1952683
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78 Errata 2132060.
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* This applies to revisions r0p0, r1p0, r1p1, and r1p2.
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* It is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* --------------------------------------------------
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*/
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func errata_a78_2132060_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2132060
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cbz x0, 1f
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/* Apply the workaround. */
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mrs x1, CORTEX_A78_CPUECTLR_EL1
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mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
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bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
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msr CORTEX_A78_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a78_2132060_wa
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func check_errata_2132060
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/* Applies to r0p0, r0p1, r1p1, and r1p2 */
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mov x1, #0x12
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b cpu_rev_var_ls
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endfunc check_errata_2132060
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/* --------------------------------------------------------------------
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* Errata Workaround for A78 Erratum 2242635.
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* This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78
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* processor and is still open.
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* The issue also exists in r0p0 but there is no fix in that revision.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------------------------
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*/
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func errata_a78_2242635_wa
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/* Compare x0 against revisions r1p0 - r1p2 */
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mov x17, x30
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bl check_errata_2242635
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cbz x0, 1f
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ldr x0, =0x5
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msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
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ldr x0, =0x10F600E000
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msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
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ldr x0, =0x10FF80E000
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msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
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ldr x0, =0x80000000003FF
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msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
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isb
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1:
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ret x17
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endfunc errata_a78_2242635_wa
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func check_errata_2242635
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/* Applies to revisions r1p0 through r1p2. */
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mov x1, #CPU_REV(1, 0)
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mov x2, #CPU_REV(1, 2)
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b cpu_rev_var_range
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endfunc check_errata_2242635
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78
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* -------------------------------------------------
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*/
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func cortex_a78_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A78_1688305
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mov x0, x18
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bl errata_a78_1688305_wa
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#endif
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#if ERRATA_A78_1941498
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mov x0, x18
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bl errata_a78_1941498_wa
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#endif
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#if ERRATA_A78_1951500
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mov x0, x18
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bl errata_a78_1951500_wa
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#endif
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#if ERRATA_A78_1821534
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mov x0, x18
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bl errata_a78_1821534_wa
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#endif
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#if ERRATA_A78_1952683
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mov x0, x18
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bl errata_a78_1952683_wa
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#endif
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#if ERRATA_A78_2132060
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mov x0, x18
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bl errata_a78_2132060_wa
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#endif
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#if ERRATA_A78_2242635
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mov x0, x18
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bl errata_a78_2242635_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el3, x0
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #CORTEX_A78_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_A78_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-A78 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a78
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret x19
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endfunc cortex_a78_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a78_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_A78_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a78_core_pwr_dwn
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/*
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* Errata printing function for cortex_a78. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_a78_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A78_1688305, cortex_a78, 1688305
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report_errata ERRATA_A78_1941498, cortex_a78, 1941498
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report_errata ERRATA_A78_1951500, cortex_a78, 1951500
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report_errata ERRATA_A78_1821534, cortex_a78, 1821534
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report_errata ERRATA_A78_1952683, cortex_a78, 1952683
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report_errata ERRATA_A78_2132060, cortex_a78, 2132060
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report_errata ERRATA_A78_2242635, cortex_a78, 2242635
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a78_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a78 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a78_regs, "aS"
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cortex_a78_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78_cpu_reg_dump
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adr x6, cortex_a78_regs
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mrs x8, CORTEX_A78_CPUECTLR_EL1
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ret
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endfunc cortex_a78_cpu_reg_dump
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declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \
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cortex_a78_reset_func, \
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cortex_a78_core_pwr_dwn
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