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https://github.com/ARM-software/arm-trusted-firmware.git
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1fe4a9d181
Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
317 lines
7.7 KiB
ArmAsm
317 lines
7.7 KiB
ArmAsm
/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a77.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1508412.
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* This applies only to revision <= r1p0 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1508412_wa
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/*
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* Compare x0 against revision r1p0
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*/
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mov x17, x30
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bl check_errata_1508412
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cbz x0, 3f
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/*
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* Compare x0 against revision r0p0
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*/
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bl check_errata_1508412_0
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cbz x0, 1f
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ldr x0, =0x0
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8400000
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msr CORTEX_A77_CPUPOR_EL3, x0
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ldr x0, =0x00FFE00000
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msr CORTEX_A77_CPUPMR_EL3, x0
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ldr x0, =0x4004003FF
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msr CORTEX_A77_CPUPCR_EL3, x0
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ldr x0, =0x1
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8C00040
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msr CORTEX_A77_CPUPOR_EL3, x0
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ldr x0, =0x00FFE00040
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msr CORTEX_A77_CPUPMR_EL3, x0
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b 2f
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1:
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ldr x0, =0x0
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8400000
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msr CORTEX_A77_CPUPOR_EL3, x0
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ldr x0, =0x00FF600000
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msr CORTEX_A77_CPUPMR_EL3, x0
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ldr x0, =0x00E8E00080
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msr CORTEX_A77_CPUPOR2_EL3, x0
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ldr x0, =0x00FFE000C0
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msr CORTEX_A77_CPUPMR2_EL3, x0
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2:
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ldr x0, =0x04004003FF
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msr CORTEX_A77_CPUPCR_EL3, x0
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isb
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3:
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ret x17
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endfunc errata_a77_1508412_wa
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func check_errata_1508412
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1508412
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func check_errata_1508412_0
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mov x1, #0x0
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b cpu_rev_var_ls
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endfunc check_errata_1508412_0
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1925769.
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* This applies to revision <= r1p1 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1925769_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1925769
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cbz x0, 1f
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/* Set bit 8 in ECTLR_EL1 */
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mrs x1, CORTEX_A77_CPUECTLR_EL1
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orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8
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msr CORTEX_A77_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1925769_wa
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func check_errata_1925769
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/* Applies to everything <= r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1925769
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1946167.
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* This applies to revision <= r1p1 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1946167_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1946167
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cbz x0, 1f
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ldr x0,=0x4
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msr CORTEX_A77_CPUPSELR_EL3,x0
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ldr x0,=0x10E3900002
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msr CORTEX_A77_CPUPOR_EL3,x0
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ldr x0,=0x10FFF00083
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msr CORTEX_A77_CPUPMR_EL3,x0
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ldr x0,=0x2001003FF
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msr CORTEX_A77_CPUPCR_EL3,x0
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ldr x0,=0x5
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msr CORTEX_A77_CPUPSELR_EL3,x0
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ldr x0,=0x10E3800082
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msr CORTEX_A77_CPUPOR_EL3,x0
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ldr x0,=0x10FFF00083
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msr CORTEX_A77_CPUPMR_EL3,x0
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ldr x0,=0x2001003FF
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msr CORTEX_A77_CPUPCR_EL3,x0
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ldr x0,=0x6
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msr CORTEX_A77_CPUPSELR_EL3,x0
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ldr x0,=0x10E3800200
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msr CORTEX_A77_CPUPOR_EL3,x0
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ldr x0,=0x10FFF003E0
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msr CORTEX_A77_CPUPMR_EL3,x0
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ldr x0,=0x2001003FF
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msr CORTEX_A77_CPUPCR_EL3,x0
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isb
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1:
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ret x17
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endfunc errata_a77_1946167_wa
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func check_errata_1946167
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/* Applies to everything <= r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1946167
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1791578.
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* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1791578_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1791578
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cbz x0, 1f
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/* Set bit 2 in ACTLR2_EL1 */
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mrs x1, CORTEX_A77_ACTLR2_EL1
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orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
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msr CORTEX_A77_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1791578_wa
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func check_errata_1791578
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/* Applies to r0p0, r1p0, and r1p1 right now */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1791578
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A77.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_a77_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A77_1508412
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mov x0, x18
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bl errata_a77_1508412_wa
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#endif
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#if ERRATA_A77_1925769
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mov x0, x18
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bl errata_a77_1925769_wa
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#endif
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#if ERRATA_A77_1946167
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mov x0, x18
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bl errata_a77_1946167_wa
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#endif
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#if ERRATA_A77_1791578
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mov x0, x18
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bl errata_a77_1791578_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-A77 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a77
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret x19
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endfunc cortex_a77_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a77_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A77_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A77_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a77_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-A77. Must follow AAPCS.
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*/
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func cortex_a77_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A77_1508412, cortex_a77, 1508412
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report_errata ERRATA_A77_1925769, cortex_a77, 1925769
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report_errata ERRATA_A77_1946167, cortex_a77, 1946167
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report_errata ERRATA_A77_1791578, cortex_a77, 1791578
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report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a77_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Cortex-A77 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a77_regs, "aS"
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cortex_a77_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a77_cpu_reg_dump
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adr x6, cortex_a77_regs
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mrs x8, CORTEX_A77_CPUECTLR_EL1
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ret
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endfunc cortex_a77_cpu_reg_dump
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declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \
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cortex_a77_reset_func, \
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cortex_a77_core_pwr_dwn
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