Amit Nagal fdf8f929df fix(xilinx): update dtb when dtb address and tf-a ddr flow is used ... Memory reservation in dtb will be done only when TF-A runs from ddr and dtb load address is provided. Otherwise prepare_dtb will simply return. Empty definition of prepare_dtb is removed. Signed-off-by: Amit Nagal <amit.nagal@amd.com> Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623		2023-08-31 09:15:26 +02:00
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common	fix(xilinx): update dtb when dtb address and tf-a ddr flow is used	2023-08-31 09:15:26 +02:00
versal	fix(versal): use correct macro name for ocm base address	2023-08-31 09:15:04 +02:00
versal_net	fix(versal-net): don't clear pending interrupts	2023-08-17 12:37:05 -07:00
zynqmp	fix(zynqmp): validate clock_id to avoid OOB variable access	2023-08-17 05:42:28 -07:00