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9202d51990
The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common/bl_common.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <common/debug.h>
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#include <errno.h>
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#include <mce.h>
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#include <mce_private.h>
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#include <memctrl.h>
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#include <common/runtime_svc.h>
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#include <tegra_private.h>
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#include <tegra_platform.h>
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#include <smmu.h>
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#include <stdbool.h>
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/*******************************************************************************
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* Tegra194 SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_GET_SMMU_PER 0xC200FF00U
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#define TEGRA_SIP_CLEAR_RAS_CORRECTED_ERRORS 0xC200FF01U
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/*******************************************************************************
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* This function is responsible for handling all T194 SiP calls
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******************************************************************************/
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int32_t plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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const void *cookie,
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void *handle,
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uint64_t flags)
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{
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int32_t ret = 0;
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uint32_t i, smmu_per[6] = {0};
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uint32_t num_smmu_devices = plat_get_num_smmu_devices();
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uint64_t per[3] = {0ULL};
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(void)x1;
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(void)x4;
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(void)cookie;
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(void)flags;
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switch (smc_fid) {
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case TEGRA_SIP_GET_SMMU_PER:
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/* make sure we dont go past the array length */
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assert(num_smmu_devices <= ARRAY_SIZE(smmu_per));
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/* read all supported SMMU_PER records */
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for (i = 0U; i < num_smmu_devices; i++) {
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smmu_per[i] = tegra_smmu_read_32(i, SMMU_GSR0_PER);
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}
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/* pack results into 3 64bit variables. */
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per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U);
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per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U);
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per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U);
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/* provide the results via X1-X3 CPU registers */
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]);
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break;
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#if RAS_FFH_SUPPORT
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case TEGRA_SIP_CLEAR_RAS_CORRECTED_ERRORS:
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{
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/*
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* clear all RAS error records for corrected errors at first.
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* x1 shall be 0 for first SMC call after FHI is asserted.
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* */
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uint64_t local_x1 = x1;
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tegra194_ras_corrected_err_clear(&local_x1);
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if (local_x1 == 0ULL) {
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/* clear HSM corrected error status after all corrected
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* RAS errors are cleared.
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*/
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mce_clear_hsm_corr_status();
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}
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, local_x1);
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break;
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}
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#endif
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default:
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ret = -ENOTSUP;
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break;
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}
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return ret;
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}
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