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90552c612e
- Define information structures for SMMU, root complex, root port and BDF mappings. - Add entries for SMMU and PCIe root complexes to Boot manifest. - Update RMMD_MANIFEST_VERSION_MINOR from 4 to 5. Change-Id: I0a76dc18edbaaff40116f376aeb56c750d57c7c1 Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
239 lines
8.4 KiB
C
239 lines
8.4 KiB
C
/*
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RMM_CORE_MANIFEST_H
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#define RMM_CORE_MANIFEST_H
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#include <assert.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <lib/cassert.h>
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#define RMMD_MANIFEST_VERSION_MAJOR U(0)
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#define RMMD_MANIFEST_VERSION_MINOR U(5)
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#define RMM_CONSOLE_MAX_NAME_LEN U(8)
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/*
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* Version encoding:
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* - Bit[31] RES0
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* - Bits [30:16] Major version
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* - Bits [15:0] Minor version
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*/
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#define SET_VERSION(_major, _minor) \
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((((_major) & 0x7FFF) << 16) | ((_minor) & 0xFFFF))
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/* Boot Manifest version */
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#define RMMD_MANIFEST_VERSION SET_VERSION( \
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RMMD_MANIFEST_VERSION_MAJOR, \
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RMMD_MANIFEST_VERSION_MINOR)
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#define RMMD_GET_MANIFEST_VERSION_MAJOR(_version) \
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((_version >> 16) & 0x7FFF)
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#define RMMD_GET_MANIFEST_VERSION_MINOR(_version) \
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(_version & 0xFFFF)
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#define PCIE_RC_INFO_VERSION_MAJOR U(0)
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#define PCIE_RC_INFO_VERSION_MINOR U(1)
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/* PCIe Root Complex info structure version */
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#define PCIE_RC_INFO_VERSION SET_VERSION( \
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PCIE_RC_INFO_VERSION_MAJOR, \
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PCIE_RC_INFO_VERSION_MINOR)
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/* Memory bank/device region structure */
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struct memory_bank {
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uint64_t base; /* Base address */
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uint64_t size; /* Size of memory bank/device region */
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};
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CASSERT(offsetof(struct memory_bank, base) == 0UL,
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rmm_manifest_base_unaligned);
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CASSERT(offsetof(struct memory_bank, size) == 8UL,
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rmm_manifest_size_unaligned);
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/* Memory/device region layout info structure */
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struct memory_info {
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uint64_t num_banks; /* Number of memory banks/device regions */
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struct memory_bank *banks; /* Pointer to memory_bank[] */
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uint64_t checksum; /* Checksum of memory_info data */
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};
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CASSERT(offsetof(struct memory_info, num_banks) == 0UL,
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rmm_manifest_num_banks_unaligned);
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CASSERT(offsetof(struct memory_info, banks) == 8UL,
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rmm_manifest_dram_data_unaligned);
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CASSERT(offsetof(struct memory_info, checksum) == 16UL,
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rmm_manifest_checksum_unaligned);
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/* Console info structure */
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struct console_info {
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uint64_t base; /* Console base address */
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uint64_t map_pages; /* Num of pages to be mapped in RMM for the console MMIO */
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char name[RMM_CONSOLE_MAX_NAME_LEN]; /* Name of console */
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uint64_t clk_in_hz; /* UART clock (in Hz) for the console */
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uint64_t baud_rate; /* Baud rate */
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uint64_t flags; /* Additional flags RES0 */
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};
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CASSERT(offsetof(struct console_info, base) == 0UL,
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rmm_manifest_console_base_unaligned);
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CASSERT(offsetof(struct console_info, map_pages) == 8UL,
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rmm_manifest_console_map_pages_unaligned);
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CASSERT(offsetof(struct console_info, name) == 16UL,
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rmm_manifest_console_name_unaligned);
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CASSERT(offsetof(struct console_info, clk_in_hz) == 24UL,
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rmm_manifest_console_clk_in_hz_unaligned);
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CASSERT(offsetof(struct console_info, baud_rate) == 32UL,
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rmm_manifest_console_baud_rate_unaligned);
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CASSERT(offsetof(struct console_info, flags) == 40UL,
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rmm_manifest_console_flags_unaligned);
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struct console_list {
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uint64_t num_consoles; /* Number of consoles */
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struct console_info *consoles; /* Pointer to console_info[] */
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uint64_t checksum; /* Checksum of console_list data */
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};
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CASSERT(offsetof(struct console_list, num_consoles) == 0UL,
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rmm_manifest_num_consoles);
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CASSERT(offsetof(struct console_list, consoles) == 8UL,
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rmm_manifest_consoles);
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CASSERT(offsetof(struct console_list, checksum) == 16UL,
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rmm_manifest_console_list_checksum);
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/* SMMUv3 Info structure */
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struct smmu_info {
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uint64_t smmu_base; /* SMMUv3 base address */
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uint64_t smmu_r_base; /* SMMUv3 Realm Pages base address */
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};
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CASSERT(offsetof(struct smmu_info, smmu_base) == 0UL,
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rmm_manifest_smmu_base);
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CASSERT(offsetof(struct smmu_info, smmu_r_base) == 8UL,
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rmm_manifest_smmu_r_base);
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/* SMMUv3 Info List structure */
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struct smmu_list {
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uint64_t num_smmus; /* Number of smmu_info entries */
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struct smmu_info *smmus; /* Pointer to smmu_info[] array */
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uint64_t checksum; /* Checksum of smmu_list data */
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};
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CASSERT(offsetof(struct smmu_list, num_smmus) == 0UL,
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rmm_manifest_num_smmus);
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CASSERT(offsetof(struct smmu_list, smmus) == 8UL,
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rmm_manifest_smmus);
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CASSERT(offsetof(struct smmu_list, checksum) == 16UL,
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rmm_manifest_smmu_list_checksum);
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/* PCIe BDF Mapping Info structure */
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struct bdf_mapping_info {
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uint16_t mapping_base; /* Base of BDF mapping (inclusive) */
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uint16_t mapping_top; /* Top of BDF mapping (exclusive) */
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uint16_t mapping_off; /* Mapping offset, as per Arm Base System Architecture: */
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/* StreamID = zero_extend(RequesterID[N-1:0]) + (1<<N)*Constant_B */
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uint16_t smmu_idx; /* SMMU index in smmu_info[] array */
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};
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CASSERT(offsetof(struct bdf_mapping_info, mapping_base) == 0UL,
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rmm_manifest_mapping_base);
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CASSERT(offsetof(struct bdf_mapping_info, mapping_top) == 2UL,
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rmm_manifest_mapping_top);
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CASSERT(offsetof(struct bdf_mapping_info, mapping_off) == 4UL,
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rmm_manifest_mapping_off);
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CASSERT(offsetof(struct bdf_mapping_info, smmu_idx) == 6UL,
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rmm_manifest_smmu_ptr);
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/* PCIe Root Port Info structure */
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struct root_port_info {
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uint16_t root_port_id; /* Root Port identifier */
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uint16_t padding; /* RES0 */
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uint32_t num_bdf_mappings; /* Number of BDF mappings */
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struct bdf_mapping_info *bdf_mappings; /* Pointer to bdf_mapping_info[] array */
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};
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CASSERT(offsetof(struct root_port_info, root_port_id) == 0UL,
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rmm_manifest_root_port_id);
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CASSERT(offsetof(struct root_port_info, num_bdf_mappings) == 4UL,
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rmm_manifest_num_bdf_mappingss);
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CASSERT(offsetof(struct root_port_info, bdf_mappings) == 8UL,
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rmm_manifest_bdf_mappings);
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/* PCIe Root Complex info structure v0.1 */
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struct root_complex_info {
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uint64_t ecam_base; /* ECAM base address. Size is implicitly 256MB */
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uint8_t segment; /* PCIe segment identifier */
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uint8_t padding[3]; /* RES0 */
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uint32_t num_root_ports; /* Number of root ports */
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struct root_port_info *root_ports; /* Pointer to root_port_info[] array */
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};
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CASSERT(offsetof(struct root_complex_info, ecam_base) == 0UL,
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rmm_manifest_ecam_base);
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CASSERT(offsetof(struct root_complex_info, segment) == 8UL,
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rmm_manifest_segment);
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CASSERT(offsetof(struct root_complex_info, num_root_ports) == 12UL,
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rmm_manifest_num_root_ports);
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CASSERT(offsetof(struct root_complex_info, root_ports) == 16UL,
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rmm_manifest_root_ports);
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/* PCIe Root Complex List structure */
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struct root_complex_list {
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uint64_t num_root_complex; /* Number of pci_rc_info entries */
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uint32_t rc_info_version; /* PCIe Root Complex info structure version */
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uint32_t padding; /* RES0 */
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struct root_complex_info *root_complex; /* Pointer to pci_rc_info[] array */
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uint64_t checksum; /* Checksum of pci_rc_list data */
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};
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CASSERT(offsetof(struct root_complex_list, num_root_complex) == 0UL,
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rmm_manifest_num_root_complex);
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CASSERT(offsetof(struct root_complex_list, rc_info_version) == 8UL,
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rmm_manifest_rc_info_version);
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CASSERT(offsetof(struct root_complex_list, root_complex) == 16UL,
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rmm_manifest_root_complex);
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CASSERT(offsetof(struct root_complex_list, checksum) == 24UL,
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rmm_manifest_root_complex_list_checksum);
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/* Boot manifest core structure as per v0.5 */
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struct rmm_manifest {
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uint32_t version; /* Manifest version */
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uint32_t padding; /* RES0 */
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uint64_t plat_data; /* Manifest platform data */
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/* Platform NS DRAM data (v0.2) */
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struct memory_info plat_dram;
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/* Platform console list (v0.3) */
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struct console_list plat_console;
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/* Platform device address ranges (v0.4) */
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struct memory_info plat_ncoh_region;
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struct memory_info plat_coh_region;
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/* Platform SMMUv3 list (v0.5) */
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struct smmu_list plat_smmu;
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/* Platform PCIe Root Complex list (v0.5) */
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struct root_complex_list plat_root_complex;
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};
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CASSERT(offsetof(struct rmm_manifest, version) == 0UL,
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rmm_manifest_version_unaligned);
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CASSERT(offsetof(struct rmm_manifest, plat_data) == 8UL,
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rmm_manifest_plat_data_unaligned);
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CASSERT(offsetof(struct rmm_manifest, plat_dram) == 16UL,
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rmm_manifest_plat_dram_unaligned);
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CASSERT(offsetof(struct rmm_manifest, plat_console) == 40UL,
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rmm_manifest_plat_console_unaligned);
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CASSERT(offsetof(struct rmm_manifest, plat_ncoh_region) == 64UL,
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rmm_manifest_plat_ncoh_region_unaligned);
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CASSERT(offsetof(struct rmm_manifest, plat_coh_region) == 88UL,
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rmm_manifest_plat_coh_region_unaligned);
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CASSERT(offsetof(struct rmm_manifest, plat_smmu) == 112UL,
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rmm_manifest_plat_smmu_unaligned);
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CASSERT(offsetof(struct rmm_manifest, plat_root_complex) == 136UL,
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rmm_manifest_plat_root_complex);
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#endif /* RMM_CORE_MANIFEST_H */
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