mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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4003ac02eb
Extend board detection with saving information about PS, PMC and RTL versions. Variables can be use to cover different behavior based on version and version information is also printed for chip identification. Change-Id: Ia37418f6a31426a5763fb89fc76fef91d09df155 Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
191 lines
6.3 KiB
C
191 lines
6.3 KiB
C
/*
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* Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DEF_H
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#define DEF_H
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#include <plat/arm/common/smccc_def.h>
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#include <plat/common/common_def.h>
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#define MAX_INTR_EL3 2U
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/* List all consoles */
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#define VERSAL2_CONSOLE_ID_none 0
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#define VERSAL2_CONSOLE_ID_pl011 1
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#define VERSAL2_CONSOLE_ID_pl011_0 1
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#define VERSAL2_CONSOLE_ID_pl011_1 2
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#define VERSAL2_CONSOLE_ID_dcc 3
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#define VERSAL2_CONSOLE_ID_dtb 4
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#define CONSOLE_IS(con) (VERSAL2_CONSOLE_ID_ ## con == VERSAL2_CONSOLE)
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/* Runtime console */
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#define RT_CONSOLE_ID_pl011 1
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#define RT_CONSOLE_ID_pl011_0 1
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#define RT_CONSOLE_ID_pl011_1 2
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#define RT_CONSOLE_ID_dcc 3
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#define RT_CONSOLE_ID_dtb 4
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#define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME)
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/* List all platforms */
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#define SILICON U(0)
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#define SPP U(1)
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#define EMU U(2)
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#define QEMU U(3)
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#define SPP_MMD U(5)
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#define EMU_MMD U(6)
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#define QEMU_COSIM U(7)
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/* For platform detection */
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#define PMC_TAP U(0xF11A0000)
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#define PMC_TAP_VERSION (PMC_TAP + 0x4U)
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# define PMC_VERSION GENMASK(7U, 0U)
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# define PS_VERSION GENMASK(15U, 8U)
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# define RTL_VERSION GENMASK(23U, 16U)
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# define PLATFORM_MASK GENMASK(27U, 24U)
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# define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
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/* Global timer reset */
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#define PSX_CRF U(0xEC200000)
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#define ACPU0_CLK_CTRL U(0x10C)
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#define ACPU_CLK_CTRL_CLKACT BIT(25)
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#define RST_APU0_OFFSET U(0x300)
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#define RST_APU_COLD_RESET BIT(0)
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#define RST_APU_WARN_RESET BIT(4)
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#define RST_APU_CLUSTER_COLD_RESET BIT(8)
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#define RST_APU_CLUSTER_WARM_RESET BIT(9)
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#define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C)
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#define APU_PCLI (0xECB10000ULL)
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#define APU_PCLI_CPU_STEP (0x30ULL)
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#define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP)
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#define APU_PCLI_CLUSTER_OFFSET U(0x8000)
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#define APU_PCLI_CLUSTER_STEP U(0x1000)
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#define PCLI_PREQ_OFFSET U(0x4)
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#define PREQ_CHANGE_REQUEST BIT(0)
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#define PCLI_PSTATE_OFFSET U(0x8)
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#define PCLI_PSTATE_VAL_SET U(0x48)
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#define PCLI_PSTATE_VAL_CLEAR U(0x38)
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/* Firmware Image Package */
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#define PRIMARY_CPU U(0)
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#define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL)
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#define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U)
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#define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL)
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#define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U)
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#define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL)
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#define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U)
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#define CORE_0_ISR_POWER_OFFSET (0x00000010ULL)
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#define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001)
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#define CORE_0_IEN_POWER_OFFSET (0x00000018ULL)
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#define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U)
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#define CORE_0_IDS_POWER_OFFSET (0x0000001CULL)
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#define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U)
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#define CORE_PWRDN_EN_BIT_MASK (0x1U)
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/*******************************************************************************
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* memory map related constants
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******************************************************************************/
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/* IPP 1.2/SPP 0.9 mapping */
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#define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */
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#define DEVICE0_SIZE U(0x08000000)
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#define DEVICE1_BASE U(0xE2000000) /* gic */
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#define DEVICE1_SIZE U(0x00800000)
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#define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */
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#define DEVICE2_SIZE U(0x01000000)
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#define CRF_BASE U(0xFD1A0000)
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#define CRF_SIZE U(0x00600000)
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#define IPI_BASE U(0xEB300000)
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#define IPI_SIZE U(0x00100000)
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/* CRL */
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#define CRL U(0xEB5E0000)
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#define CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C)
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#define CRL_RST_TIMESTAMP_OFFSET U(0x348)
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#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U)
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/* IOU SCNTRS */
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#define IOU_SCNTRS U(0xEC920000)
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#define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
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#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
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#define IOU_SCNTRS_CONTROL_EN U(1)
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#define APU_CLUSTER0 U(0xECC00000)
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#define APU_RVBAR_L_0 U(0x40)
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#define APU_RVBAR_H_0 U(0x44)
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#define APU_CLUSTER_STEP U(0x100000)
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#define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504)
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#define PMXC_IOU_SLCR_SRAM_CSR U(0xF106104C)
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#define PMXC_IOU_SLCR_PHY_RESET U(0xF1061050)
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#define PMXC_IOU_SLCR_TX_RX_CONFIG_RDY U(0xF1061054)
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#define PMXC_CRP_RST_UFS U(0xF1260340)
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/*******************************************************************************
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* IRQ constants
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******************************************************************************/
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#define IRQ_SEC_PHY_TIMER U(29)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define UART0_BASE U(0xF1920000)
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#define UART1_BASE U(0xF1930000)
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#define UART_BAUDRATE 115200
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#if CONSOLE_IS(pl011) || CONSOLE_IS(dtb)
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#define UART_BASE UART0_BASE
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# define UART_TYPE CONSOLE_PL011
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#elif CONSOLE_IS(pl011_1)
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#define UART_BASE UART1_BASE
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# define UART_TYPE CONSOLE_PL011
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#elif CONSOLE_IS(dcc)
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# define UART_BASE 0x0
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# define UART_TYPE CONSOLE_DCC
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#elif CONSOLE_IS(none)
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# define UART_TYPE CONSOLE_NONE
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#else
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# error "invalid VERSAL2_CONSOLE"
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#endif
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/* Runtime console */
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#if defined(CONSOLE_RUNTIME)
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#if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb)
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# define RT_UART_BASE UART0_BASE
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# define RT_UART_TYPE CONSOLE_PL011
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#elif RT_CONSOLE_IS(pl011_1)
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# define RT_UART_BASE UART1_BASE
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# define RT_UART_TYPE CONSOLE_PL011
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#elif RT_CONSOLE_IS(dcc)
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# define RT_UART_BASE 0x0
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# define RT_UART_TYPE CONSOLE_DCC
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#else
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# error "invalid CONSOLE_RUNTIME"
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#endif
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#endif
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#endif /* DEF_H */
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