mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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06077161e9
We have do something for clocks gate. Fox example as the below: susped: clk_gate_con_save(); clk_gate_con_disable(); resume: clk_gate_con_restore(); -- SO, add the plls_suspend_prepare() and plls_resume_finish() are not necessary to S2R, that will save S2R time if remove them. BRANCH=none BUG=chrome-os-partner:58870,chrome-os-partner:55934 TEST=build kevin, two dogfooders with suspend_stress_test passing 3000 cycles and still going on. Change-Id: Icfbabc0b3ea8d2b5108d4f3de99a803b6d459669 Signed-off-by: Caesar Wang <wxt@rock-chips.com>
362 lines
11 KiB
C
362 lines
11 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SOC_H__
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#define __SOC_H__
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#define GLB_SRST_FST_CFG_VAL 0xfdb9
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#define GLB_SRST_SND_CFG_VAL 0xeca8
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#define PMUCRU_PPLL_CON(n) ((n) * 4)
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#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
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#define PLL_MODE_MSK 0x03
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#define PLL_MODE_SHIFT 0x08
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#define PLL_BYPASS_MSK 0x01
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#define PLL_BYPASS_SHIFT 0x01
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#define PLL_PWRDN_MSK 0x01
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#define PLL_PWRDN_SHIFT 0x0
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#define PLL_BYPASS BIT(1)
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#define PLL_PWRDN BIT(0)
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#define NO_PLL_BYPASS (0x00)
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#define NO_PLL_PWRDN (0x00)
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#define FBDIV(n) ((0xfff << 16) | n)
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#define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12))
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#define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8))
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#define REFDIV(n) ((0x3F << 16) | n)
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#define PLL_LOCK(n) ((n >> 31) & 0x1)
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#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
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PLL_MODE_MSK, PLL_MODE_SHIFT)
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#define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\
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PLL_MODE_MSK, PLL_MODE_SHIFT)
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#define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT)
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#define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT)
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#define PLL_CON_COUNT 0x06
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#define CRU_CLKSEL_COUNT 108
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#define CRU_CLKSEL_CON(n) (0x100 + (n) * 4)
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#define PMUCRU_CLKSEL_CONUT 0x06
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#define PMUCRU_CLKSEL_OFFSET 0x080
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#define REG_SIZE 0x04
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#define REG_SOC_WMSK 0xffff0000
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#define CLK_GATE_MASK 0x01
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#define SGRF_SOC_COUNT 0x17
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#define PMUCRU_GATE_COUNT 0x03
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#define CRU_GATE_COUNT 0x23
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#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
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#define CRU_GATE_CON(n) (0x300 + (n) * 4)
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enum plls_id {
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ALPLL_ID = 0,
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ABPLL_ID,
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DPLL_ID,
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CPLL_ID,
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GPLL_ID,
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NPLL_ID,
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VPLL_ID,
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PPLL_ID,
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END_PLL_ID,
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};
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#define CLST_L_CPUS_MSK (0xf)
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#define CLST_B_CPUS_MSK (0x3)
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enum pll_work_mode {
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SLOW_MODE = 0x00,
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NORMAL_MODE = 0x01,
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DEEP_SLOW_MODE = 0x02,
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};
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enum glb_sft_reset {
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PMU_RST_BY_FIRST_SFT,
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PMU_RST_BY_SECOND_SFT = BIT(2),
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PMU_RST_NOT_BY_SFT = BIT(3),
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};
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struct deepsleep_data_s {
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uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
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uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT];
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uint32_t cru_clksel_con[CRU_CLKSEL_COUNT];
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uint32_t cru_gate_con[CRU_GATE_COUNT];
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uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
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uint32_t sgrf_con[SGRF_SOC_COUNT];
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};
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/**************************************************
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* pmugrf reg, offset
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**************************************************/
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#define PMUGRF_OSREG(n) (0x300 + (n) * 4)
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/**************************************************
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* DCF reg, offset
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**************************************************/
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#define DCF_DCF_CTRL 0x0
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#define DCF_DCF_ADDR 0x8
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#define DCF_DCF_ISR 0xc
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#define DCF_DCF_TOSET 0x14
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#define DCF_DCF_TOCMD 0x18
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#define DCF_DCF_CMD_CFG 0x1c
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/* DCF_DCF_ISR */
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#define DCF_TIMEOUT (1 << 2)
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#define DCF_ERR (1 << 1)
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#define DCF_DONE (1 << 0)
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/* DCF_DCF_CTRL */
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#define DCF_VOP_HW_EN (1 << 2)
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#define DCF_STOP (1 << 1)
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#define DCF_START (1 << 0)
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#define CYCL_24M_CNT_US(us) (24 * us)
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#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
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#define CYCL_32K_CNT_MS(ms) (ms * 32)
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/**************************************************
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* secure timer
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**************************************************/
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/* chanal0~5 */
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#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
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/* chanal6~11 */
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#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n))
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/* low 32 bits */
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#define TIMER_END_COUNT0 0x00
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/* high 32 bits */
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#define TIMER_END_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0C
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/* low 32 bits */
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#define TIMER_INIT_COUNT0 0x10
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/* high 32 bits */
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#define TIMER_INIT_COUNT1 0x14
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#define TIMER_INTSTATUS 0x18
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#define TIMER_CONTROL_REG 0x1c
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#define TIMER_EN 0x1
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#define TIMER_FMODE (0x0 << 1)
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#define TIMER_RMODE (0x1 << 1)
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/**************************************************
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* secure WDT
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**************************************************/
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#define WDT_CM0_EN 0x0
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#define WDT_CM0_DIS 0x1
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#define WDT_CA53_EN 0x0
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#define WDT_CA53_DIS 0x1
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#define PCLK_WDT_CA53_GATE_SHIFT 8
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#define PCLK_WDT_CM0_GATE_SHIFT 10
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#define WDT_CA53_1BIT_MASK 0x1
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#define WDT_CM0_1BIT_MASK 0x1
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/**************************************************
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* cru reg, offset
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**************************************************/
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#define CRU_SOFTRST_CON(n) (0x400 + (n) * 4)
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#define CRU_DMAC0_RST BIT_WITH_WMSK(3)
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/* reset release*/
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#define CRU_DMAC0_RST_RLS WMSK_BIT(3)
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#define CRU_DMAC1_RST BIT_WITH_WMSK(4)
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/* reset release*/
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#define CRU_DMAC1_RST_RLS WMSK_BIT(4)
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#define CRU_GLB_RST_CON 0x0510
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#define CRU_GLB_SRST_FST 0x0500
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#define CRU_GLB_SRST_SND 0x0504
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#define CRU_CLKGATE_CON(n) (0x300 + n * 4)
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#define PCLK_GPIO2_GATE_SHIFT 3
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#define PCLK_GPIO3_GATE_SHIFT 4
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#define PCLK_GPIO4_GATE_SHIFT 5
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/**************************************************
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* pmu cru reg, offset
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**************************************************/
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#define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4)
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/* reset hold*/
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#define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6)
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/* reset hold release*/
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#define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6)
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#define CRU_PMU_WDTRST_MSK (0x1 << 4)
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#define CRU_PMU_WDTRST_EN 0x0
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#define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2)
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#define CRU_PMU_FIRST_SFTRST_EN 0x0
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#define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4)
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#define PCLK_GPIO0_GATE_SHIFT 3
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#define PCLK_GPIO1_GATE_SHIFT 4
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/**************************************************
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* sgrf reg, offset
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**************************************************/
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#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4)
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#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4)
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#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4)
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#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4)
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#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4)
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#define SGRF_DDRRGN_CON0_16(n) ((n) * 4)
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#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4)
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/* security config for master */
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#define SGRF_SOC_CON_WMSK 0xffff0000
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/* All of master in ns */
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#define SGRF_SOC_ALLMST_NS 0xffff
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/* security config for slave */
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#define SGRF_SLV_S_WMSK 0xffff0000
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#define SGRF_SLV_S_ALL_NS 0x0
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/* security config pmu slave ip */
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/* All of slaves is ns */
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#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)
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/* slaves secure attr is configed */
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#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
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#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)
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#define SGRF_PMUSRAM_S BIT(8)
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#define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \
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SGRF_PMUSRAM_S)
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/* ddr region */
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#define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */
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#define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */
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#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */
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/* The MST access the ddr rgn n with secure attribution */
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#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n))
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/* bits[16:8]*/
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#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8)
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/* dmac to periph s or ns*/
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#define SGRF_DMAC_CFG_S 0xffff0000
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#define DMAC1_RGN_NS 0xff000000
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#define DMAC0_RGN_NS 0x00ff0000
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#define DMAC0_BOOT_CFG_NS 0xfffffff8
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#define DMAC0_BOOT_PERIPH_NS 0xffff0fff
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#define DMAC0_BOOT_ADDR_NS 0xffff0000
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#define DMAC1_BOOT_CFG_NS 0xffff0008
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#define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff
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#define DMAC1_BOOT_ADDR_NS 0xffff0000
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#define DMAC1_BOOT_PERIPH_H_NS 0xffffffff
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#define DMAC1_BOOT_IRQ_NS 0xffffffff
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#define CPU_BOOT_ADDR_WMASK 0xffff0000
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#define CPU_BOOT_ADDR_ALIGN 16
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#define GRF_IOMUX_2BIT_MASK 0x3
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#define GRF_IOMUX_GPIO 0x0
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#define GRF_GPIO4C2_IOMUX_SHIFT 4
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#define GRF_GPIO4C2_IOMUX_PWM 0x1
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#define GRF_GPIO4C6_IOMUX_SHIFT 12
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#define GRF_GPIO4C6_IOMUX_PWM 0x1
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#define PWM_CNT(n) (0x0000 + 0x10 * (n))
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#define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n))
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#define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n))
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#define PWM_CTRL(n) (0x000c + 0x10 * (n))
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#define PWM_DISABLE (0 << 0)
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#define PWM_ENABLE (1 << 0)
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/* grf reg offset */
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#define GRF_DDRC0_CON0 0xe380
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#define GRF_DDRC0_CON1 0xe384
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#define GRF_DDRC1_CON0 0xe388
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#define GRF_DDRC1_CON1 0xe38c
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#define PMUCRU_CLKSEL_CON0 0x0080
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#define PMUCRU_CLKGATE_CON2 0x0108
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#define PMUCRU_SOFTRST_CON0 0x0110
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#define PMUCRU_GATEDIS_CON0 0x0130
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#define SGRF_SOC_CON6 0x0e018
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#define SGRF_PERILP_CON0 0x08100
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#define SGRF_PERILP_CON(n) (SGRF_PERILP_CON0 + (n) * 4)
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#define SGRF_PMU_CON0 0x0c100
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#define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4)
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#define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4)
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/*
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* When system reset in running state, we want the cpus to be reboot
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* from maskrom (system reboot),
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* the pmusgrf reset-hold bits needs to be released.
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* When system wake up from system deep suspend, some soc will be reset
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* when waked up,
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* we want the bootcpu to be reboot from pmusram,
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* the pmusgrf reset-hold bits needs to be held.
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*/
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static inline void pmu_sgrf_rst_hld_release(void)
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{
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mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
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CRU_PMU_SGRF_RST_RLS);
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}
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static inline void pmu_sgrf_rst_hld(void)
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{
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mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
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CRU_PMU_SGRF_RST_HOLD);
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}
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/* funciton*/
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void __dead2 soc_global_soft_reset(void);
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void secure_watchdog_disable();
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void secure_watchdog_restore();
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void disable_dvfs_plls(void);
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void disable_nodvfs_plls(void);
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void enable_dvfs_plls(void);
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void enable_nodvfs_plls(void);
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void prepare_abpll_for_ddrctrl(void);
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void restore_abpll(void);
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void restore_dpll(void);
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void clk_gate_con_save(void);
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void clk_gate_con_disable(void);
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void clk_gate_con_restore(void);
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void sgrf_init(void);
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#endif /* __SOC_H__ */
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