Boyan Karatotev 46e92f2862 fix(sme): add missing ISBs ... EL3 is configured to trap accesses to SME registers (via CPTR_EL3.ESM=0). To allow SME instructions, this needs to be temporarily disabled before changing system registers. If the PE delays the effects of writes to system registers then accessing the SME registers will trap without an isb. This patch adds the isb to restore functionality. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I8ee5ecaec978dde2525631daa682a182ad8f7f04		2022-10-13 13:51:05 +01:00
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amu	fix(amu): limit virtual offset register access to NS world	2022-04-28 20:30:42 +02:00
brbe	feat(brbe): add brbe under feature detection mechanism	2022-06-06 11:43:03 +01:00
mpam	refactor(mpam): remove initialization of EL2 registers when EL2 is used	2022-04-12 17:41:51 +02:00
mtpmu	Add support for FEAT_MTPMU for Armv8.6	2020-12-11 12:49:20 +00:00
pauth	TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U	2019-10-03 14:43:55 +01:00
ras	lib/extensions/ras: fix bug of binary search	2021-01-14 09:27:16 +08:00
sme	fix(sme): add missing ISBs	2022-10-13 13:51:05 +01:00
spe	feat(spe): add support for FEAT_SPEv1p2	2022-02-10 09:30:13 +00:00
sve	feat(sve): support full SVE vector length	2022-07-08 17:17:11 +01:00
sys_reg_trace	feat(sys_reg_trace): enable trace system registers access from lower NS ELs	2021-08-26 09:29:51 +01:00
trbe	feat(trbe): add trbe under feature detection mechanism	2022-06-06 11:43:14 +01:00
trf	feat(trf): enable trace filter control register access from lower NS EL	2021-08-26 09:32:35 +01:00