mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00
8d69a03f6a
- Check at link-time that bootloader images will fit in memory
at run time and that they won't overlap each other.
- Remove text and rodata orphan sections.
- Define new linker symbols to remove the need for platform setup
code to know the order of sections.
- Reduce the size of the raw binary images by cutting some sections
out of the disk image and allocating them at load time, whenever
possible.
- Rework alignment constraints on sections.
- Remove unused linker symbols.
- Homogenize linker symbols names across all BLs.
- Add some comments in the linker scripts.
Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9
248 lines
5.7 KiB
ArmAsm
248 lines
5.7 KiB
ArmAsm
/*
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* Copyright (c) 2013, ARM Limited. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <runtime_svc.h>
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.globl runtime_exceptions
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#include <asm_macros.S>
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.section .text, "ax"; .align 11
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.align 7
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runtime_exceptions:
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/* -----------------------------------------------------
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* Current EL with _sp_el0 : 0x0 - 0x180
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* -----------------------------------------------------
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*/
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sync_exception_sp_el0:
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exception_entry save_regs
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mov x0, #SYNC_EXCEPTION_SP_EL0
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mov x1, sp
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bl sync_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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irq_sp_el0:
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exception_entry save_regs
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mov x0, #IRQ_SP_EL0
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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fiq_sp_el0:
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exception_entry save_regs
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mov x0, #FIQ_SP_EL0
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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serror_sp_el0:
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exception_entry save_regs
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mov x0, #SERROR_SP_EL0
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x380
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_sp_elx:
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exception_entry save_regs
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mov x0, #SYNC_EXCEPTION_SP_ELX
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mov x1, sp
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bl sync_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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irq_sp_elx:
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exception_entry save_regs
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mov x0, #IRQ_SP_ELX
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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fiq_sp_elx:
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exception_entry save_regs
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mov x0, #FIQ_SP_ELX
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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serror_sp_elx:
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exception_entry save_regs
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mov x0, #SERROR_SP_ELX
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x580
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch64:
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exception_entry save_regs
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mov x0, #SYNC_EXCEPTION_AARCH64
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mov x1, sp
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bl sync_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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irq_aarch64:
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exception_entry save_regs
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mov x0, #IRQ_AARCH64
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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fiq_aarch64:
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exception_entry save_regs
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mov x0, #FIQ_AARCH64
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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serror_aarch64:
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exception_entry save_regs
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mov x0, #IRQ_AARCH32
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x780
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch32:
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exception_entry save_regs
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mov x0, #SYNC_EXCEPTION_AARCH32
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mov x1, sp
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bl sync_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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irq_aarch32:
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exception_entry save_regs
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mov x0, #IRQ_AARCH32
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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fiq_aarch32:
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exception_entry save_regs
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mov x0, #FIQ_AARCH32
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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serror_aarch32:
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exception_entry save_regs
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mov x0, #SERROR_AARCH32
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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save_regs:; .type save_regs, %function
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sub sp, sp, #0x100
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stp x0, x1, [sp, #0x0]
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stp x2, x3, [sp, #0x10]
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stp x4, x5, [sp, #0x20]
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stp x6, x7, [sp, #0x30]
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stp x8, x9, [sp, #0x40]
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stp x10, x11, [sp, #0x50]
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stp x12, x13, [sp, #0x60]
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stp x14, x15, [sp, #0x70]
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stp x16, x17, [sp, #0x80]
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stp x18, x19, [sp, #0x90]
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stp x20, x21, [sp, #0xa0]
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stp x22, x23, [sp, #0xb0]
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stp x24, x25, [sp, #0xc0]
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stp x26, x27, [sp, #0xd0]
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mrs x0, sp_el0
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stp x28, x0, [sp, #0xe0]
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mrs x0, spsr_el3
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str x0, [sp, #0xf0]
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ret
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restore_regs:; .type restore_regs, %function
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ldr x9, [sp, #0xf0]
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msr spsr_el3, x9
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ldp x28, x9, [sp, #0xe0]
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msr sp_el0, x9
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ldp x26, x27, [sp, #0xd0]
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ldp x24, x25, [sp, #0xc0]
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ldp x22, x23, [sp, #0xb0]
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ldp x20, x21, [sp, #0xa0]
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ldp x18, x19, [sp, #0x90]
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ldp x16, x17, [sp, #0x80]
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ldp x14, x15, [sp, #0x70]
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ldp x12, x13, [sp, #0x60]
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ldp x10, x11, [sp, #0x50]
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ldp x8, x9, [sp, #0x40]
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ldp x6, x7, [sp, #0x30]
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ldp x4, x5, [sp, #0x20]
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ldp x2, x3, [sp, #0x10]
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ldp x0, x1, [sp, #0x0]
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add sp, sp, #0x100
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ret
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