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https://github.com/ARM-software/arm-trusted-firmware.git
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8cec598ba3
The current code does not always use data and instruction barriers as required by the architecture and frequently uses barriers excessively due to their inclusion in all of the write_*() helper functions. Barriers should be used explicitly in assembler or C code when modifying processor state that requires the barriers in order to enable review of correctness of the code. This patch removes the barriers from the helper functions and introduces them as necessary elsewhere in the code. PORTING NOTE: check any port of Trusted Firmware for use of system register helper functions for reliance on the previous barrier behaviour and add explicit barriers as necessary. Fixes ARM-software/tf-issues#92 Change-Id: Ie63e187404ff10e0bdcb39292dd9066cb84c53bf
77 lines
2.9 KiB
C
77 lines
2.9 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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/*******************************************************************************
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* Function that does the first bit of architectural setup that affects
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* execution in the non-secure address space.
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******************************************************************************/
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void bl1_arch_setup(void)
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{
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unsigned long tmp_reg = 0;
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/* Enable alignment checks and set the exception endianess to LE */
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tmp_reg = read_sctlr_el3();
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tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT);
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tmp_reg &= ~SCTLR_EE_BIT;
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write_sctlr_el3(tmp_reg);
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isb();
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/*
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* Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route
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* external abort and SError interrupts to EL3
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*/
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tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT |
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SCR_FIQ_BIT;
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write_scr(tmp_reg);
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/*
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* Enable SError and Debug exceptions
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*/
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enable_serror();
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enable_debug_exceptions();
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}
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/*******************************************************************************
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* Set the Secure EL1 required architectural state
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******************************************************************************/
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void bl1_arch_next_el_setup(void) {
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unsigned long next_sctlr;
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/* Use the same endianness than the current BL */
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next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
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/* Set SCTLR Secure EL1 */
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next_sctlr |= SCTLR_EL1_RES1;
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write_sctlr_el1(next_sctlr);
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}
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