Soby Mathew 8cd16e6b5b Build option to include AArch32 registers in cpu context ... The system registers that are saved and restored in CPU context include AArch32 systems registers like SPSR_ABT, SPSR_UND, SPSR_IRQ, SPSR_FIQ, DACR32_EL2, IFSR32_EL2 and FPEXC32_EL2. Accessing these registers on an AArch64-only (i.e. on hardware that does not implement AArch32, or at least not at EL1 and higher ELs) platform leads to an exception. This patch introduces the build option `CTX_INCLUDE_AARCH32_REGS` to specify whether to include these AArch32 systems registers in the cpu context or not. By default this build option is set to 1 to ensure compatibility. AArch64-only platforms must set it to 0. A runtime check is added in BL1 and BL31 cold boot path to verify this. Fixes ARM-software/tf-issues#386 Change-Id: I720cdbd7ed7f7d8516635a2ec80d025f478b95ee		2016-06-03 10:50:52 +01:00
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aarch64	Add 32 bit version of plat_get_syscnt_freq	2016-05-20 15:29:03 +01:00
bl31.ld.S	Remove dashes from image names: 'BL3-x' --> 'BL3x'	2015-12-14 12:31:37 +00:00
bl31.mk	Miscellaneous doc fixes for v1.2	2015-12-21 18:10:12 +00:00
bl31_context_mgmt.c	Move context management code to common location	2015-12-09 17:41:18 +00:00
bl31_main.c	Build option to include AArch32 registers in cpu context	2016-06-03 10:50:52 +01:00
cpu_data_array.c	Rework the crash reporting in BL3-1 to use less stack	2014-07-28 11:03:20 +01:00
interrupt_mgmt.c	Enable support for EL3 interrupt in IMF	2015-12-09 09:58:17 +00:00
runtime_svc.c	Add support for %p in tf_printf()	2016-02-18 09:45:39 +00:00