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8c5fe0b5b9
This patch moves the bakery locks out of coherent memory to normal memory. This implies that the lock information needs to be placed on a separate cache line for each cpu. Hence the bakery_lock_info_t structure is allocated in the per-cpu data so as to minimize memory wastage. A similar platform per-cpu data is introduced for the platform locks. As a result of the above changes, the bakery lock api is completely changed. Earlier, a reference to the lock structure was passed to the lock implementation. Now a unique-id (essentially an index into the per-cpu data array) and an offset into the per-cpu data for bakery_info_t needs to be passed to the lock implementation. Change-Id: I1e76216277448713c6c98b4c2de4fb54198b39e0
77 lines
3.1 KiB
Makefile
77 lines
3.1 KiB
Makefile
#
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# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# Neither the name of ARM nor the names of its contributors may be used
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# to endorse or promote products derived from this software without specific
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# prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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BL31_SOURCES += bl31/bl31_main.c \
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bl31/context_mgmt.c \
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bl31/cpu_data_array.c \
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bl31/runtime_svc.c \
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bl31/interrupt_mgmt.c \
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bl31/aarch64/bl31_arch_setup.c \
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bl31/aarch64/bl31_entrypoint.S \
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bl31/aarch64/context.S \
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bl31/aarch64/cpu_data.S \
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bl31/aarch64/runtime_exceptions.S \
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bl31/aarch64/crash_reporting.S \
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lib/cpus/aarch64/cpu_helpers.S \
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lib/locks/exclusive/spinlock.S \
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services/std_svc/std_svc_setup.c \
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services/std_svc/psci/psci_afflvl_off.c \
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services/std_svc/psci/psci_afflvl_on.c \
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services/std_svc/psci/psci_afflvl_suspend.c \
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services/std_svc/psci/psci_common.c \
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services/std_svc/psci/psci_entry.S \
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services/std_svc/psci/psci_helpers.S \
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services/std_svc/psci/psci_main.c \
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services/std_svc/psci/psci_setup.c \
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services/std_svc/psci/psci_system_off.c
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ifeq (${USE_COHERENT_MEM}, 1)
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BL31_SOURCES += lib/locks/bakery/bakery_lock_coherent.c
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else
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BL31_SOURCES += lib/locks/bakery/bakery_lock_normal.c
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endif
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BL31_LINKERFILE := bl31/bl31.ld.S
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# Flag used by the generic interrupt management framework to determine if
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# upon the assertion of an interrupt, it should pass the interrupt id or not
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IMF_READ_INTERRUPT_ID := 0
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$(eval $(call assert_boolean,IMF_READ_INTERRUPT_ID))
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$(eval $(call add_define,IMF_READ_INTERRUPT_ID))
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# Flag used to inidicate if Crash reporting via console should be included
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# in BL3-1. This defaults to being present in DEBUG builds only
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ifndef CRASH_REPORTING
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CRASH_REPORTING := $(DEBUG)
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endif
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$(eval $(call assert_boolean,CRASH_REPORTING))
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$(eval $(call add_define,CRASH_REPORTING))
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