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arm-trusted-firmware/plat/intel/soc
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Jit Loon Lim 8a0a006af3 fix(altera): add in support for agilex5 b0 jtag id 
Support Agilex5 B0 jtag id for fpga reconfig.

Change-Id: I4efb5a046a0f11009a1f08412ff0e48f376c94e1
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
2025-02-10 12:22:06 +08:00
..
agilex fix(intel): update warm reset routine and bootscratch register usage 2025-01-13 16:31:42 +08:00
agilex5 fix(altera): add in support for agilex5 b0 jtag id 2025-02-10 12:22:06 +08:00
common fix(altera): add in support for agilex5 b0 jtag id 2025-02-10 12:22:06 +08:00
n5x fix(intel): update warm reset routine and bootscratch register usage 2025-01-13 16:31:42 +08:00
stratix10 fix(intel): update warm reset routine and bootscratch register usage 2025-01-13 16:31:42 +08:00