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4c700c1563
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
152 lines
4.3 KiB
ArmAsm
152 lines
4.3 KiB
ArmAsm
/*
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* Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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#include <services/arm_arch_svc.h>
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.globl wa_cve_2017_5715_mmu_vbar
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#define ESR_EL3_A64_SMC0 0x5e000000
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#define ESR_EL3_A32_SMC0 0x4e000000
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vector_base wa_cve_2017_5715_mmu_vbar
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.macro apply_cve_2017_5715_wa _is_sync_exception _esr_el3_val
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stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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mrs x1, sctlr_el3
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/* Disable MMU */
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bic x1, x1, #SCTLR_M_BIT
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msr sctlr_el3, x1
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isb
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/* Enable MMU */
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orr x1, x1, #SCTLR_M_BIT
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msr sctlr_el3, x1
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/*
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* Defer ISB to avoid synchronizing twice in case we hit
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* the workaround SMC call which will implicitly synchronize
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* because of the ERET instruction.
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*/
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/*
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* Ensure SMC is coming from A64/A32 state on #0
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* with W0 = SMCCC_ARCH_WORKAROUND_1 or W0 = SMCCC_ARCH_WORKAROUND_3
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*
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* This sequence evaluates as:
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* (W0==SMCCC_ARCH_WORKAROUND_1) || (W0==SMCCC_ARCH_WORKAROUND_3) ?
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* (ESR_EL3==SMC#0) : (NE)
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* allowing use of a single branch operation
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*/
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.if \_is_sync_exception
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orr w1, wzr, #SMCCC_ARCH_WORKAROUND_1
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cmp w0, w1
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orr w1, wzr, #SMCCC_ARCH_WORKAROUND_3
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ccmp w0, w1, #4, ne
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mrs x0, esr_el3
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mov_imm w1, \_esr_el3_val
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ccmp w0, w1, #0, eq
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/* Static predictor will predict a fall through */
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bne 1f
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exception_return
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1:
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.endif
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/*
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* Synchronize now to enable the MMU. This is required
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* to ensure the load pair below reads the data stored earlier.
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*/
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isb
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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.endm
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200
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* ---------------------------------------------------------------------
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*/
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vector_entry mmu_sync_exception_sp_el0
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b sync_exception_sp_el0
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end_vector_entry mmu_sync_exception_sp_el0
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vector_entry mmu_irq_sp_el0
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b irq_sp_el0
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end_vector_entry mmu_irq_sp_el0
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vector_entry mmu_fiq_sp_el0
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b fiq_sp_el0
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end_vector_entry mmu_fiq_sp_el0
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vector_entry mmu_serror_sp_el0
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b serror_sp_el0
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end_vector_entry mmu_serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400
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* ---------------------------------------------------------------------
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*/
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vector_entry mmu_sync_exception_sp_elx
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b sync_exception_sp_elx
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end_vector_entry mmu_sync_exception_sp_elx
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vector_entry mmu_irq_sp_elx
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b irq_sp_elx
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end_vector_entry mmu_irq_sp_elx
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vector_entry mmu_fiq_sp_elx
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b fiq_sp_elx
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end_vector_entry mmu_fiq_sp_elx
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vector_entry mmu_serror_sp_elx
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b serror_sp_elx
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end_vector_entry mmu_serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* ---------------------------------------------------------------------
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*/
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vector_entry mmu_sync_exception_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A64_SMC0
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b sync_exception_aarch64
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end_vector_entry mmu_sync_exception_aarch64
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vector_entry mmu_irq_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b irq_aarch64
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end_vector_entry mmu_irq_aarch64
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vector_entry mmu_fiq_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b fiq_aarch64
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end_vector_entry mmu_fiq_aarch64
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vector_entry mmu_serror_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b serror_aarch64
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end_vector_entry mmu_serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry mmu_sync_exception_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A32_SMC0
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b sync_exception_aarch32
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end_vector_entry mmu_sync_exception_aarch32
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vector_entry mmu_irq_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b irq_aarch32
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end_vector_entry mmu_irq_aarch32
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vector_entry mmu_fiq_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b fiq_aarch32
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end_vector_entry mmu_fiq_aarch32
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vector_entry mmu_serror_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b serror_aarch32
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end_vector_entry mmu_serror_aarch32
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